公开(公告)号：US08274072B2

公开(公告)日：2012-09-25

申请号：US13401967

申请日：2012-02-22

Applicant: Zhihong Chen ,  Dechao Guo ,  Shu-jen Han ,  Kai Zhao

Inventor： Zhihong Chen ,  Dechao Guo ,  Shu-jen Han ,  Kai Zhao

IPC: H01L29/76

CPC classification number: H01L29/1606 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/7781 ,  H01L29/78684

Abstract: A carbon-based field effect transistor (FET) includes a substrate; a carbon layer located on the substrate, the carbon layer comprising a channel region, and source and drain regions located on either side of the channel region; a gate electrode located on the channel region in the carbon layer, the gate electrode comprising a first dielectric layer, a gate metal layer located on the first dielectric layer, and a nitride layer located on the gate metal layer; and a spacer comprising a second dielectric layer located adjacent to the gate electrode, wherein the spacer is not located on the carbon layer.

Abstract translation: 碳基场效应晶体管（FET）包括基板; 位于所述基板上的碳层，所述碳层包括沟道区，以及位于所述沟道区两侧的源区和漏区; 位于所述碳层中的沟道区上的栅电极，所述栅电极包括第一电介质层，位于所述第一电介质层上的栅极金属层和位于所述栅极金属层上的氮化物层; 以及间隔件，其包括邻近所述栅电极的第二电介质层，其中所述间隔物不位于所述碳层上。

公开(公告)号：US20120108017A1

公开(公告)日：2012-05-03

申请号：US13347014

申请日：2012-01-10

Applicant: Brian J. Greene ,  Michael P. Chudzik ,  Shu-Jen Han ,  William K. Henson ,  Yue Liang ,  Edward P. Maciejewski ,  Myung-Hee Na ,  Edward J. Nowak ,  Xiaojun Yu

Inventor： Brian J. Greene ,  Michael P. Chudzik ,  Shu-Jen Han ,  William K. Henson ,  Yue Liang ,  Edward P. Maciejewski ,  Myung-Hee Na ,  Edward J. Nowak ,  Xiaojun Yu

IPC: H01L21/782 ,  H01L21/8238

CPC classification number: H01L21/823462 ,  H01L21/28229 ,  H01L21/84 ,  H01L27/1203

Abstract: Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.

Abstract translation: 在掺杂半导体阱上形成多种类型的栅叠层。 在掺杂半导体阱上形成高介电常数（高k）栅极电介质。 在一个器件区域中形成金属栅极层，而在其他器件区域中暴露高k栅极电介质。 在其他器件区域中形成具有不同厚度的阈值电压调节氧化物层。 然后在阈值电压调整氧化物层上形成导电栅极材料层。 一种类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质。 其他类型的场效应晶体管包括包括高k栅极电介质部分的栅极电介质和具有不同厚度的第一阈值电压调整氧化物部分。 具有不同阈值电压的场效应晶体管通过采用具有相同掺杂剂浓度的不同栅极电介质叠层和掺杂半导体阱来提供。

公开(公告)号：US08105893B2

公开(公告)日：2012-01-31

申请号：US12621216

申请日：2009-11-18

Applicant: Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

Inventor： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

IPC: H01L21/8238

CPC classification number: H01L21/76224 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

Abstract: A method of forming diffusion sidewalls in a semiconductor structure and a semiconductor structure having diffusion sidewalls includes etching a trench into a semiconductor substrate to form first and second active regions, lining each trench with an oxide liner along exposed sidewalls of an active silicon region (RX) of the first and second active regions, removing the oxide liner formed along the exposed sidewalls of the RX region of one of the first and second active regions, forming diffusion sidewalls by epitaxially growing in-situ doped material within the exposed sidewalls of the RX region of the one of the first and second active regions, and forming an isolation region within the trench between the first and second active regions to electrically isolate the first and second active regions from each other.

Abstract translation: 在半导体结构中形成扩散侧壁的方法和具有扩散侧壁的半导体结构的方法包括将沟槽蚀刻到半导体衬底中以形成第一和第二有源区，沿着有源硅区（RX ）去除沿着第一和第二有源区域之一的RX区域的暴露的侧壁形成的氧化物衬垫，通过在RX的暴露侧壁内外延生长原位掺杂材料来形成扩散侧壁 区域，并且在第一和第二有源区域之间的沟槽内形成隔离区域，以将第一和第二有源区域彼此电隔离。

公开(公告)号：US20120007054A1

公开(公告)日：2012-01-12

申请号：US12832224

申请日：2010-07-08

Applicant: Josephine B. Chang ,  Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin

Inventor： Josephine B. Chang ,  Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin

IPC: H01L29/76 ,  H01L29/78 ,  H01L27/12 ,  H01L29/24 ,  H01L21/86 ,  H01L21/04

CPC classification number: H01L29/1606 ,  B82Y10/00 ,  H01L29/165 ,  H01L29/41733 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/66431 ,  H01L29/66742 ,  H01L29/7781 ,  H01L29/78 ,  H01L29/78684 ,  H01L51/0048

Abstract: A method for forming a semiconductor device includes forming a carbon material on a substrate, forming a gate stack on the carbon material, removing a portion of the substrate to form at least one cavity defined by a portion of the carbon material and the substrate, and forming a conductive contact in the at least one cavity.

Abstract translation: 一种用于形成半导体器件的方法包括在基片上形成碳材料，在碳材料上形成栅叠层，去除基片的一部分以形成由碳材料和基片的一部分限定的至少一个空腔，以及 在所述至少一个空腔中形成导电接触。

公开(公告)号：US20110248362A1

公开(公告)日：2011-10-13

申请号：US12755752

申请日：2010-04-07

Applicant: Dechao Guo ,  Wilfried E.A. Haensch ,  Shu-Jen Han ,  Chung-Hsun Lin

Inventor： Dechao Guo ,  Wilfried E.A. Haensch ,  Shu-Jen Han ,  Chung-Hsun Lin

IPC: H01L29/78 ,  H01L21/28

CPC classification number: H01L21/28008 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/76897 ,  H01L29/517 ,  H01L29/66507 ,  H01L29/66545

Abstract: A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer.

Abstract translation: 提供了一种形成具有自对准接触的栅极结构的方法，并且包括将牺牲层和次级层顺序地沉积到设置在栅极结构的位置处的多晶硅上，封装牺牲层，第二层和聚 -Si，通过形成在次级层中的开口去除牺牲层，并在至少由牺牲层正式占据的空间内形成硅化物。

公开(公告)号：US20110223612A1

公开(公告)日：2011-09-15

申请号：US13046368

申请日：2011-03-11

Applicant: Shan X. Wang ,  Richard S. Gaster ,  Liang Xu ,  Shu-Jen Han ,  Robert Wilson

Inventor： Shan X. Wang ,  Richard S. Gaster ,  Liang Xu ,  Shu-Jen Han ,  Robert Wilson

IPC: G01N33/557 ,  G01N33/566 ,  G01N33/68 ,  G01N27/72

CPC classification number: G01N27/745 ,  G01N33/557 ,  Y10T436/143333

Abstract: Methods for quantitatively determining a binding kinetic parameter of a molecular binding interaction are provided. Aspects of embodiments of the methods include: producing a magnetic sensor device including a magnetic sensor in contact with an assay mixture including a magnetically labeled molecule to produce a detectable molecular binding interaction; obtaining a real-time signal from the magnetic sensor; and quantitatively determining a binding kinetics parameter of the molecular binding interaction from the real-time signal. Also provided are systems and kits configured for use in the methods.

Abstract translation: 提供了定量测定分子结合相互作用的结合动力学参数的方法。 所述方法的实施方案的方面包括：产生包括与包含磁性标记分子的测定混合物接触以产生可检测分子结合相互作用的磁传感器的磁传感器装置; 从磁传感器获取实时信号; 并从实时信号中定量测定分子结合相互作用的结合动力学参数。 还提供了配置用于该方法的系统和套件。

公开(公告)号：US20110215300A1

公开(公告)日：2011-09-08

申请号：US12719058

申请日：2010-03-08

Applicant: Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

Inventor： Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin ,  Ning Su

IPC: H01L27/088 ,  H01L21/8256

CPC classification number: H01L27/0688 ,  H01L29/1606 ,  Y10S977/755

Abstract: A three-dimensional (3D) integrated circuit (IC) structure includes a first layer of graphene formed over a substrate; a first level of one or more active devices formed using the first layer of graphene; an insulating layer formed over the first level of one or more active devices; a second layer of graphene formed over the insulating layer; and a second level of one or more active devices formed using the second layer of graphene, the second level of one or more active devices electrically interconnected with the first level of one or more active devices.

Abstract translation: 三维（3D）集成电路（IC）结构包括在衬底上形成的第一层石墨烯; 使用第一层石墨烯形成的一个或多个有源器件的第一级; 绝缘层，形成在一个或多个有源器件的第一级上; 在所述绝缘层上形成的第二层石墨烯; 以及使用第二层石墨烯形成的一个或多个有源器件的第二电平，一个或多个有源器件的第二电平与一个或多个有源器件的第一电平电互连。

公开(公告)号：US09082856B2

公开(公告)日：2015-07-14

申请号：US13613198

申请日：2012-09-13

Applicant: Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

Inventor： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/16 ,  H01L29/49

CPC classification number: H01L29/66045 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02527 ,  H01L21/044 ,  H01L29/1606 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/517 ,  H01L29/66015 ,  H01L29/66742 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78684

Abstract: An electronic device comprises an insulator, a local first gate embedded in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator, a first dielectric layer formed over the first gate and insulator, and a channel. The channel comprises a bilayer graphene layer formed on the first dielectric layer. The first dielectric layer provides a substantially flat surface on which the channel is formed. A second dielectric layer formed over the bilayer graphene layer and a local second gate formed over the second dielectric layer. Each of the local first and second gates is capacitively coupled to the channel of the bilayer graphene layer. The local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer.

Abstract translation: 电子设备包括绝缘体，嵌入在绝缘体中的局部第一栅极，第一栅极的顶表面与绝缘体的表面基本共面;形成在第一栅极和绝缘体上的第一介电层，以及沟道。 通道包括形成在第一介电层上的双层石墨烯层。 第一电介质层提供基本上平坦的表面，在其上形成沟道。 形成在双层石墨烯层上的第二介电层和在第二介电层上形成的局部第二栅极。 局部第一和第二栅极中的每一个电容耦合到双层石墨烯层的沟道。 局部第一和第二栅极形成第一对栅极以局部控制双层石墨烯层的第一部分。

公开(公告)号：US09064842B2

公开(公告)日：2015-06-23

申请号：US13425302

申请日：2012-03-20

Applicant: Ageeth Anke Bol ,  Aaron Daniel Franklin ,  Shu-Jen Han

Inventor： Ageeth Anke Bol ,  Aaron Daniel Franklin ,  Shu-Jen Han

IPC: H01L29/778 ,  H01L21/335 ,  H01L29/417 ,  H01L21/02 ,  C01B31/04 ,  H01L29/16

CPC classification number: H01L29/41733 ,  C01B32/19 ,  H01L21/02527 ,  H01L29/1606 ,  H01L29/778 ,  Y10S977/734

Abstract: A semiconductor device includes a substrate, first plural contacts formed in the substrate, a graphene layer formed on the substrate and on the first plural contacts and second plural contacts formed on the graphene layer such that the graphene layer is formed between the first plural contacts and the second plural contacts.

Abstract translation: 半导体器件包括衬底，形成在衬底中的第一多个触点，形成在衬底上的石墨烯层和在第一多个触点上形成的第二多个触点和形成在石墨烯层上的第二多个触点，使得石墨烯层形成在第一多个触点和 第二个复数接触。

公开(公告)号：US09045842B2

公开(公告)日：2015-06-02

申请号：US13617727

申请日：2012-09-14

Applicant: Shu-Jen Han ,  Lian Guo ,  Xuesong Li

Inventor： Shu-Jen Han ,  Lian Guo ,  Xuesong Li

IPC: C25F7/00 ,  C25F5/00 ,  B32B38/10 ,  C25F3/02 ,  C01B31/04

CPC classification number: C25F7/00 ,  B32B38/10 ,  C01B32/186 ,  C25F3/02 ,  C25F5/00

Abstract: An electroplating etching apparatus includes a power to output current, and a container configured to contain an electrolyte. A cathode is coupled to the container and configured to fluidly communicate with the electrolyte. An anode is electrically connected to the output, and includes a graphene layer. A metal substrate layer is formed on the graphene layer, and is etched from the graphene layer in response to the current flowing through the anode.

Abstract translation: 电镀蚀刻装置包括输出电流的电力，以及容纳电解质的容器。 阴极耦合到容器并且构造成与电解液流体连通。 阳极电连接到输出端，并且包括石墨烯层。 在石墨烯层上形成金属基底层，并响应于流过阳极的电流从石墨烯层中蚀刻出金属基底层。