公开(公告)号：US20250096008A1

公开(公告)日：2025-03-20

申请号：US18965221

申请日：2024-12-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die and a first interconnect structure coupled to the integrated circuit die. Through-vias are also coupled to the first interconnect structure. A molding material is disposed around the integrated circuit die and the through-vias over the first interconnect structure. The molding material has a pit disposed therein. A recovery material is disposed within the pit in the molding material. A second interconnect structure is disposed over the molding material, the recovery material, the integrated circuit die, and the through-vias.

公开(公告)号：US12256552B2

公开(公告)日：2025-03-18

申请号：US18525301

申请日：2023-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Sheng Chang

IPC: H10B51/30 ,  G11C11/22 ,  H01L49/02

Abstract: A semiconductor device includes a ferroelectric field-effect transistor (FeFET), wherein the FeFET includes a substrate; a source region in the substrate; a drain region in the substrate; and a gate structure over the substrate and between the source region and the drain region. The gate structure includes a gate dielectric layer over the substrate; a ferroelectric film over the gate dielectric layer; and a gate electrode over the ferroelectric film.

公开(公告)号：US12255171B2

公开(公告)日：2025-03-18

申请号：US17412768

申请日：2021-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-De Chen ,  Yun Chen Teng ,  Chen-Fong Tsai ,  Jyh-Cherng Sheu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L23/00 ,  H01L21/683

Abstract: In an embodiment, a wafer bonding system includes a chamber, a gas inlet and a gas outlet configured to control a pressure of the chamber to be in a range from 1×10−2 mbar to 1520 torr, a first wafer chuck having a first surface to support a first wafer, and a second wafer chuck having a second surface to support a second wafer, the second surface being opposite the first surface, the second wafer chuck and the first wafer chuck being movable relative to each other, wherein the second surface that supports the second wafer is divided into zones, wherein a vacuum pressure of each zone is controlled independently of other zones.

公开(公告)号：US12255102B2

公开(公告)日：2025-03-18

申请号：US18524710

申请日：2023-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Lun Chang ,  Jiun-Ming Kuo ,  Ji-Yin Tsai ,  Yuan-Ching Peng

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/306 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

Abstract: A first layer is formed over a substrate; a second layer is formed over the first layer; and a third layer is formed over the second layer. The first and third layers each have a first semiconductor element; the second layer has a second semiconductor element different from the first semiconductor element. The second layer has the second semiconductor element at a first concentration in a first region and at a second concentration in a second region of the second layer. A source/drain trench is formed in a region of the stack to expose side surfaces of the layers. A first portion of the second layer is removed from the exposed side surface to form a gap between the first and the third layers. A spacer is formed in the gap. A source/drain feature is formed in the source/drain trench and on a sidewall of the spacer.

公开(公告)号：US12255101B2

公开(公告)日：2025-03-18

申请号：US18401780

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chang Lin ,  Chun-Feng Nieh ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: A nanoFET transistor includes doped channel junctions at either end of a channel region for one or more nanosheets of the nanoFET transistor. The channel junctions are formed by a iterative recessing and implanting process which is performed as recesses are made for the source/drain regions. The implanted doped channel junctions can be controlled to achieve a desired lateral straggling of the doped channel junctions.

公开(公告)号：US12253796B2

公开(公告)日：2025-03-18

申请号：US18545948

申请日：2023-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Yue Lin

IPC: G03F1/24

Abstract: A photolithography mask includes a substrate, a reflective multilayer structure over the substrate, an adhesion layer over the reflective multilayer structure, a capping layer over the adhesion layer, and a patterned absorber layer over the capping layer. The capping layer includes a non-crystalline conductive material.

公开(公告)号：US20250089332A1

公开(公告)日：2025-03-13

申请号：US18962707

申请日：2024-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Qiang WU ,  Kuo-An LIU ,  Chan-Lon YANG ,  Bharath Kumar PULICHERLA ,  Li-Te LIN ,  Chung-Cheng WU ,  Gwan-Sin CHANG ,  Pinyen LIN

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/40 ,  H01L29/49 ,  H01L29/78

Abstract: A semiconductor device includes a substrate having a semiconductor fin. A gate structure is over the semiconductor fin, in which the gate structure has a tapered profile and comprises a gate dielectric. A work function metal layer is over the gate dielectric, and a filling metal is over the work function metal layer. A gate spacer is along a sidewall of the gate structure, in which the work function metal layer is in contact with the gate dielectric and a top portion of the gate spacer. An epitaxy structure is over the semiconductor fin.

公开(公告)号：US20250089319A1

公开(公告)日：2025-03-13

申请号：US18962876

申请日：2024-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jhon-Jhy LIAW

IPC: H01L29/08 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  H10B10/00

Abstract: An integrated circuit (IC) structure includes first and second semiconductor channel patterns extending over a substrate. From a plan view, the second semiconductor channel pattern has a longitudinal axis aligned with a longitudinal axis of the first semiconductor channel pattern, the first semiconductor channel pattern has a first longitudinal side and a second longitudinal side separated from the first longitudinal side by a first distance, and the second channel pattern has a third longitudinal side and a fourth longitudinal side separated from the third longitudinal side by a second distance less than the first distance.

公开(公告)号：US20250089313A1

公开(公告)日：2025-03-13

申请号：US18463466

申请日：2023-09-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Fong Tsai ,  Han-De Chen ,  Chi On Chui

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/04 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A method includes: epitaxially growing a first multi-layer stack over a first substrate; epitaxially growing a second multi-layer stack over a second substrate; and bonding the first multi-layer stack to the second multi-layer stack. The first substrate and the second substrate have different crystalline orientations. The method further includes patterning the first multi-layer stack and the second multi-layer stack to form a fin, the fin comprising a plurality of lower nanostructures alternatingly stacked with first dummy nanostructures and a plurality of upper nanostructures alternatingly stacked with second dummy nanostructure; replacing the first dummy nanostructures with a first gate stack, the first gate stack surrounding each of the plurality of lower nanostructures; and replacing the second dummy nanostructures with a second gate stack, the second gate stack surrounding each of the plurality of upper nanostructures.

公开(公告)号：US20250087639A1

公开(公告)日：2025-03-13

申请号：US18401846

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ke-Gang Wen ,  Yu-Bey Wu ,  Tsung-Chieh Hsiao ,  Liang-Wei Wang ,  Dian-Hau Chen

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48

Abstract: A method includes forming first integrated circuits on a front side of a semiconductor substrate of a first device die, forming a trench capacitor extending from a backside of the semiconductor substrate into the semiconductor substrate, and forming a first through-via and a second through-via penetrating through the semiconductor substrate. The trench capacitor is electrically coupled between the first through-via and the second through-via. A second device die is bonded to the first die. The second device die includes second integrated circuits, and power nodes of the second integrated circuits are electrically coupled to the first through-via and the second through-via.