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    Fabrication method for device structure having transparent dielectric substrate
    41.
    发明授权
    Fabrication method for device structure having transparent dielectric substrate 有权
    具有透明电介质基板的器件结构的制造方法

    公开(公告)号：US08076220B2

    公开(公告)日：2011-12-13

    申请号：US12779244

    申请日：2010-05-13

    Applicant: Toshiyuki Nakamura ,  Satoshi Machida ,  Sachiko Yabe ,  Takashi Taguchi

    Inventor： Toshiyuki Nakamura ,  Satoshi Machida ,  Sachiko Yabe ,  Takashi Taguchi

    IPC: H01L21/36

    CPC classification number: H01L21/86

    Abstract: A semiconductor device has a transparent dielectric substrate such as a sapphire substrate. To enable fabrication equipment to detect the presence of the substrate optically, the back surface of the substrate is coated with a triple-layer light-reflecting film, preferably a film in which a silicon oxide or silicon nitride layer is sandwiched between polycrystalline silicon layers. This structure provides high reflectance with a combined film thickness of less than half a micrometer.

    Abstract translation: 半导体器件具有诸如蓝宝石衬底的透明电介质衬底。 为了使制造设备能够光学地检测衬底的存在，衬底的背面涂覆有三层光反射膜，优选其中氧化硅或氮化硅层夹在多晶硅层之间的膜。 该结构提供具有小于半微米的组合膜厚度的高反射率。

    FABRICATION METHOD FOR DEVICE STRUCTURE HAVING TRANSPARENT DIELECTRIC SUBSTRATE
    43.
    发明申请
    FABRICATION METHOD FOR DEVICE STRUCTURE HAVING TRANSPARENT DIELECTRIC SUBSTRATE 有权
    具有透明基板的器件结构的制造方法

    公开(公告)号：US20100240195A1

    公开(公告)日：2010-09-23

    申请号：US12779244

    申请日：2010-05-13

    Applicant: Toshiyuki Nakamura ,  Satoshi Machida ,  Sachiko Yabe ,  Takashi Taguchi

    Inventor： Toshiyuki Nakamura ,  Satoshi Machida ,  Sachiko Yabe ,  Takashi Taguchi

    IPC: H01L21/302

    CPC classification number: H01L21/86

    Abstract: A semiconductor device has a transparent dielectric substrate such as a sapphire substrate. To enable fabrication equipment to detect the presence of the substrate optically, the back surface of the substrate is coated with a triple-layer light-reflecting film, preferably a film in which a silicon oxide or silicon nitride layer is sandwiched between polycrystalline silicon layers. This structure provides high reflectance with a combined film thickness of less than half a micrometer.

    Abstract translation: 半导体器件具有诸如蓝宝石衬底的透明电介质衬底。 为了使制造设备能够光学地检测衬底的存在，衬底的背面涂覆有三层光反射膜，优选其中氧化硅或氮化硅层夹在多晶硅层之间的膜。 该结构提供具有小于半微米的组合膜厚度的高反射率。

    Dielectric substrate with reflecting films
    44.
    发明授权
    Dielectric substrate with reflecting films 有权
    具反光膜的介质基片

    公开(公告)号：US07745880B2

    公开(公告)日：2010-06-29

    申请号：US11252632

    申请日：2005-10-19

    Applicant: Toshiyuki Nakamura ,  Satoshi Machida ,  Sachiko Yabe ,  Takashi Taguchi

    Inventor： Toshiyuki Nakamura ,  Satoshi Machida ,  Sachiko Yabe ,  Takashi Taguchi

    IPC: H01L31/0232

    CPC classification number: H01L21/86

    Abstract: A semiconductor device has a transparent dielectric substrate such as a sapphire substrate. To enable fabrication equipment to detect the presence of the substrate optically, the back surface of the substrate is coated with a triple-layer light-reflecting film, preferably a film in which a silicon oxide or silicon nitride layer is sandwiched between polycrystalline silicon layers. This structure provides high reflectance with a combined film thickness of less than half a micrometer.

    Abstract translation: 半导体器件具有诸如蓝宝石衬底的透明电介质衬底。 为了使制造设备能够光学地检测衬底的存在，衬底的背面涂覆有三层光反射膜，优选其中氧化硅或氮化硅层夹在多晶硅层之间的膜。 该结构提供具有小于半微米的组合膜厚度的高反射率。

    Method of forming alignment marks for semiconductor device fabrication
    46.
    发明授权
    Method of forming alignment marks for semiconductor device fabrication 有权
    形成用于半导体器件制造的对准标记的方法

    公开(公告)号：US07332405B2

    公开(公告)日：2008-02-19

    申请号：US11048891

    申请日：2005-02-03

    Applicant: Sachiko Yabe ,  Takashi Taguchi ,  Minoru Watanabe

    Inventor： Sachiko Yabe ,  Takashi Taguchi ,  Minoru Watanabe

    IPC: H01L21/76

    CPC classification number: H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor integrated circuit is fabricated in a substrate having a semiconductor layer and an underlying insulator layer. The fabrication process includes a step of locally oxidizing the semiconductor layer to form a field oxide, during which step the semiconductor layer is protected by a nitride film. The nitride film has both openings to permit local oxidization in the integrated circuit area, and an opening defining an alignment mark adjacent to the circuit area. The alignment mark may be formed either in the semiconductor and insulator layers, or in a part of the nitride film left after the nitride film is removed from the circuit area. In either case, the edge height of the alignment mark is not limited by the thickness of the semiconductor layer. Using the nitride layer to define both the alignment mark and the field oxide reduces the necessary number of fabrication steps.

    Abstract translation: 在具有半导体层和下层绝缘体层的衬底中制造半导体集成电路。 制造工艺包括将半导体层局部氧化以形成场氧化物的步骤，在该步骤期间半导体层被氮化物膜保护。 氮化物膜具有两个开口以允许集成电路区域中的局部氧化，以及限定与电路区域相邻的对准标记的开口。 对准标记可以形成在半导体层和绝缘体层中，或者在从电路区域去除氮化物膜之后残留的氮化膜的一部分中。 在任一情况下，对准标记的边缘高度不受半导体层的厚度的限制。 使用氮化物层来限定对准标记和场氧化物两者减少了必要数量的制造步骤。

    Linear grating formation method
    47.
    发明授权
    Linear grating formation method 失效
    线性光栅形成方法

    公开(公告)号：US07312019B2

    公开(公告)日：2007-12-25

    申请号：US11066495

    申请日：2005-02-28

    Applicant: Suguru Sasaki ,  Satoshi Machida ,  Takashi Taguchi

    Inventor： Suguru Sasaki ,  Satoshi Machida ,  Takashi Taguchi

    IPC: H01L21/027

    CPC classification number: G02B5/1857 ,  G03F7/0005 ,  G03F7/0035

    Abstract: A method of forming a linear grating is disclosed. When forming a first resist pattern covering certain surface regions of a substrate, the mask pattern position is shifted and the first resist pattern is formed such that the trench in the target region is completely filled with the first resist pattern even when an error in positioning occurs. The surface of the first resist pattern is etched, and a lower resist pattern is left to the same level as the uppermost step of the silicon substrate. On top of this, an upper resist pattern having the same pattern as the first resist pattern is formed. At this time, the mask pattern position is shifted and the exposure dose is adjusted such that one edge of the upper resist pattern is positioned on the lower resist pattern, and the other edge is positioned in a prescribed region border portion. The lower resist pattern and upper resist pattern are used as a mask to etch the silicon substrate.

    Abstract translation: 公开了一种形成线性光栅的方法。 当形成覆盖基板的某些表面区域的第一抗蚀剂图案时，掩模图案位置移动，并且形成第一抗蚀剂图案，使得即使当定位错误发生时，目标区域中的沟槽也完全被第一抗蚀剂图案填充 。 蚀刻第一抗蚀剂图案的表面，并且将下抗蚀剂图案保留到与硅衬底的最上层步骤相同的水平。 此外，形成具有与第一抗蚀剂图案相同的图案的上抗蚀剂图案。 此时，掩模图案位置移动，并且调整曝光剂量使得上抗蚀剂图案的一个边缘位于下抗蚀剂图案上，另一边缘位于规定区域边界部分中。 下抗蚀剂图案和上抗蚀剂图案用作掩模以蚀刻硅衬底。

    Semiconductor device and semiconductor wafer
    48.
    发明授权
    Semiconductor device and semiconductor wafer 有权
    半导体器件和半导体晶片

    公开(公告)号：US07180199B2

    公开(公告)日：2007-02-20

    申请号：US11345288

    申请日：2006-02-02

    Applicant: Satoshi Machida ,  Takashi Taguchi ,  Noboru Uchida ,  Suguru Sasaki

    Inventor： Satoshi Machida ,  Takashi Taguchi ,  Noboru Uchida ,  Suguru Sasaki

    IPC: H01L23/544

    CPC classification number: H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device comprises a semiconductor substrate having a first surface and a second surface, and a first multilayer laminated structure film which is formed in the first surface of the semiconductor substrate and has a first layer having a first refractive index, a second layer formed on the first layer and having a second refractive index lower than the first refractive index, and a third layer formed on the second layer and having a third refractive index higher than the second refractive index, and in which the thicknesses of the respective layers are respectively thicknesses calculated by (2N+1)λ/(4n) where the wavelength of light used for detecting the first multilayer laminated structure film is defined as λ, the refractive indices of the respective layers are defined as n, and N is defined as 0 or a natural number.

    Abstract translation: 半导体器件包括具有第一表面和第二表面的半导体衬底和形成在半导体衬底的第一表面中并且具有第一折射率的第一层的第一多层叠结构膜， 所述第一层具有低于所述第一折射率的第二折射率，以及形成在所述第二层上并具有高于所述第二折射率的第三折射率的第三层，并且其中各层的厚度分别为厚度 （2N + 1）λ/（4n）计算，其中将用于检测第一多层叠结构膜的光的波长定义为λ，将各层的折射率定义为n，将N定义为0或 自然数。

    Semiconductor device and semiconductor wafer
    49.
    发明申请
    Semiconductor device and semiconductor wafer 有权
    半导体器件和半导体晶片

    公开(公告)号：US20060197237A1

    公开(公告)日：2006-09-07

    申请号：US11345288

    申请日：2006-02-02

    Applicant: Satoshi Machida ,  Takashi Taguchi ,  Noboru Uchida ,  Suguru Sasaki

    Inventor： Satoshi Machida ,  Takashi Taguchi ,  Noboru Uchida ,  Suguru Sasaki

    IPC: H01L23/544

    CPC classification number: H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device comprises a semiconductor substrate having a first surface and a second surface, and a first multilayer laminated structure film which is formed in the first surface of the semiconductor substrate and has a first layer having a first refractive index, a second layer formed on the first layer and having a second refractive index lower than the first refractive index, and a third layer formed on the second layer and having a third refractive index higher than the second refractive index, and in which the thicknesses of the respective layers are respectively thicknesses calculated by (2N+1)λ/(4n) where the wavelength of light used for detecting the first multilayer laminated structure film is defined as λ, the refractive indices of the respective layers are defined as n, and N is defined as 0 or a natural number.

    Abstract translation: 半导体器件包括具有第一表面和第二表面的半导体衬底和形成在半导体衬底的第一表面中并且具有第一折射率的第一层的第一多层叠结构膜， 所述第一层具有低于所述第一折射率的第二折射率，以及形成在所述第二层上并具有高于所述第二折射率的第三折射率的第三层，并且其中各层的厚度分别为厚度 （2N + 1）λ/（4n）计算，其中将用于检测第一多层叠结构膜的光的波长定义为λ，将各层的折射率定义为n，将N定义为0或 自然数。

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