公开(公告)号：US20060102975A1

公开(公告)日：2006-05-18

申请号：US11252632

申请日：2005-10-19

申请人： Toshiyuki Nakamura ,  Satoshi Machida ,  Sachiko Yabe ,  Takashi Taguchi

发明人： Toshiyuki Nakamura ,  Satoshi Machida ,  Sachiko Yabe ,  Takashi Taguchi

IPC分类号： H01L31/0232

CPC分类号： H01L21/86

摘要： A semiconductor device has a transparent dielectric substrate such as a sapphire substrate. To enable fabrication equipment to detect the presence of the substrate optically, the back surface of the substrate is coated with a triple-layer light-reflecting film, preferably a film in which a silicon oxide or silicon nitride layer is sandwiched between polycrystalline silicon layers. This structure provides high reflectance with a combined film thickness of less than half a micrometer.

摘要翻译： 半导体器件具有诸如蓝宝石衬底的透明电介质衬底。 为了使制造设备能够光学地检测衬底的存在，衬底的背面涂覆有三层光反射膜，优选其中氧化硅或氮化硅层夹在多晶硅层之间的膜。 该结构提供具有小于半微米的组合膜厚度的高反射率。

公开(公告)号：US08076220B2

公开(公告)日：2011-12-13

申请号：US12779244

申请日：2010-05-13

申请人： Toshiyuki Nakamura ,  Satoshi Machida ,  Sachiko Yabe ,  Takashi Taguchi

发明人： Toshiyuki Nakamura ,  Satoshi Machida ,  Sachiko Yabe ,  Takashi Taguchi

IPC分类号： H01L21/36

CPC分类号： H01L21/86

摘要： A semiconductor device has a transparent dielectric substrate such as a sapphire substrate. To enable fabrication equipment to detect the presence of the substrate optically, the back surface of the substrate is coated with a triple-layer light-reflecting film, preferably a film in which a silicon oxide or silicon nitride layer is sandwiched between polycrystalline silicon layers. This structure provides high reflectance with a combined film thickness of less than half a micrometer.

摘要翻译： 半导体器件具有诸如蓝宝石衬底的透明电介质衬底。 为了使制造设备能够光学地检测衬底的存在，衬底的背面涂覆有三层光反射膜，优选其中氧化硅或氮化硅层夹在多晶硅层之间的膜。 该结构提供具有小于半微米的组合膜厚度的高反射率。

公开(公告)号：US20100240195A1

公开(公告)日：2010-09-23

申请号：US12779244

申请日：2010-05-13

申请人： Toshiyuki Nakamura ,  Satoshi Machida ,  Sachiko Yabe ,  Takashi Taguchi

发明人： Toshiyuki Nakamura ,  Satoshi Machida ,  Sachiko Yabe ,  Takashi Taguchi

IPC分类号： H01L21/302

CPC分类号： H01L21/86

摘要： A semiconductor device has a transparent dielectric substrate such as a sapphire substrate. To enable fabrication equipment to detect the presence of the substrate optically, the back surface of the substrate is coated with a triple-layer light-reflecting film, preferably a film in which a silicon oxide or silicon nitride layer is sandwiched between polycrystalline silicon layers. This structure provides high reflectance with a combined film thickness of less than half a micrometer.

摘要翻译： 半导体器件具有诸如蓝宝石衬底的透明电介质衬底。 为了使制造设备能够光学地检测衬底的存在，衬底的背面涂覆有三层光反射膜，优选其中氧化硅或氮化硅层夹在多晶硅层之间的膜。 该结构提供具有小于半微米的组合膜厚度的高反射率。

公开(公告)号：US07745880B2

公开(公告)日：2010-06-29

申请号：US11252632

申请日：2005-10-19

申请人： Toshiyuki Nakamura ,  Satoshi Machida ,  Sachiko Yabe ,  Takashi Taguchi

发明人： Toshiyuki Nakamura ,  Satoshi Machida ,  Sachiko Yabe ,  Takashi Taguchi

IPC分类号： H01L31/0232

CPC分类号： H01L21/86

摘要： A semiconductor device has a transparent dielectric substrate such as a sapphire substrate. To enable fabrication equipment to detect the presence of the substrate optically, the back surface of the substrate is coated with a triple-layer light-reflecting film, preferably a film in which a silicon oxide or silicon nitride layer is sandwiched between polycrystalline silicon layers. This structure provides high reflectance with a combined film thickness of less than half a micrometer.

摘要翻译： 半导体器件具有诸如蓝宝石衬底的透明电介质衬底。 为了使制造设备能够光学地检测衬底的存在，衬底的背面涂覆有三层光反射膜，优选其中氧化硅或氮化硅层夹在多晶硅层之间的膜。 该结构提供具有小于半微米的组合膜厚度的高反射率。

公开(公告)号：US07312019B2

公开(公告)日：2007-12-25

申请号：US11066495

申请日：2005-02-28

申请人： Suguru Sasaki ,  Satoshi Machida ,  Takashi Taguchi

发明人： Suguru Sasaki ,  Satoshi Machida ,  Takashi Taguchi

IPC分类号： H01L21/027

CPC分类号： G02B5/1857 ,  G03F7/0005 ,  G03F7/0035

摘要： A method of forming a linear grating is disclosed. When forming a first resist pattern covering certain surface regions of a substrate, the mask pattern position is shifted and the first resist pattern is formed such that the trench in the target region is completely filled with the first resist pattern even when an error in positioning occurs. The surface of the first resist pattern is etched, and a lower resist pattern is left to the same level as the uppermost step of the silicon substrate. On top of this, an upper resist pattern having the same pattern as the first resist pattern is formed. At this time, the mask pattern position is shifted and the exposure dose is adjusted such that one edge of the upper resist pattern is positioned on the lower resist pattern, and the other edge is positioned in a prescribed region border portion. The lower resist pattern and upper resist pattern are used as a mask to etch the silicon substrate.

摘要翻译： 公开了一种形成线性光栅的方法。 当形成覆盖基板的某些表面区域的第一抗蚀剂图案时，掩模图案位置移动，并且形成第一抗蚀剂图案，使得即使当定位错误发生时，目标区域中的沟槽也完全被第一抗蚀剂图案填充 。 蚀刻第一抗蚀剂图案的表面，并且将下抗蚀剂图案保留到与硅衬底的最上层步骤相同的水平。 此外，形成具有与第一抗蚀剂图案相同的图案的上抗蚀剂图案。 此时，掩模图案位置移动，并且调整曝光剂量使得上抗蚀剂图案的一个边缘位于下抗蚀剂图案上，另一边缘位于规定区域边界部分中。 下抗蚀剂图案和上抗蚀剂图案用作掩模以蚀刻硅衬底。

公开(公告)号：US07180199B2

公开(公告)日：2007-02-20

申请号：US11345288

申请日：2006-02-02

申请人： Satoshi Machida ,  Takashi Taguchi ,  Noboru Uchida ,  Suguru Sasaki

发明人： Satoshi Machida ,  Takashi Taguchi ,  Noboru Uchida ,  Suguru Sasaki

IPC分类号： H01L23/544

CPC分类号： H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprises a semiconductor substrate having a first surface and a second surface, and a first multilayer laminated structure film which is formed in the first surface of the semiconductor substrate and has a first layer having a first refractive index, a second layer formed on the first layer and having a second refractive index lower than the first refractive index, and a third layer formed on the second layer and having a third refractive index higher than the second refractive index, and in which the thicknesses of the respective layers are respectively thicknesses calculated by (2N+1)λ/(4n) where the wavelength of light used for detecting the first multilayer laminated structure film is defined as λ, the refractive indices of the respective layers are defined as n, and N is defined as 0 or a natural number.

摘要翻译： 半导体器件包括具有第一表面和第二表面的半导体衬底和形成在半导体衬底的第一表面中并且具有第一折射率的第一层的第一多层叠结构膜， 所述第一层具有低于所述第一折射率的第二折射率，以及形成在所述第二层上并具有高于所述第二折射率的第三折射率的第三层，并且其中各层的厚度分别为厚度 （2N + 1）λ/（4n）计算，其中将用于检测第一多层叠结构膜的光的波长定义为λ，将各层的折射率定义为n，将N定义为0或 自然数。

公开(公告)号：US20060197237A1

公开(公告)日：2006-09-07

申请号：US11345288

申请日：2006-02-02

申请人： Satoshi Machida ,  Takashi Taguchi ,  Noboru Uchida ,  Suguru Sasaki

发明人： Satoshi Machida ,  Takashi Taguchi ,  Noboru Uchida ,  Suguru Sasaki

IPC分类号： H01L23/544

CPC分类号： H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprises a semiconductor substrate having a first surface and a second surface, and a first multilayer laminated structure film which is formed in the first surface of the semiconductor substrate and has a first layer having a first refractive index, a second layer formed on the first layer and having a second refractive index lower than the first refractive index, and a third layer formed on the second layer and having a third refractive index higher than the second refractive index, and in which the thicknesses of the respective layers are respectively thicknesses calculated by (2N+1)λ/(4n) where the wavelength of light used for detecting the first multilayer laminated structure film is defined as λ, the refractive indices of the respective layers are defined as n, and N is defined as 0 or a natural number.

摘要翻译： 半导体器件包括具有第一表面和第二表面的半导体衬底和形成在半导体衬底的第一表面中并且具有第一折射率的第一层的第一多层叠结构膜， 所述第一层具有低于所述第一折射率的第二折射率，以及形成在所述第二层上并具有高于所述第二折射率的第三折射率的第三层，并且其中各层的厚度分别为厚度 （2N + 1）λ/（4n）计算，其中将用于检测第一多层叠结构膜的光的波长定义为λ，将各层的折射率定义为n，将N定义为0或 自然数。

公开(公告)号：US20050196709A1

公开(公告)日：2005-09-08

申请号：US11066495

申请日：2005-02-28

申请人： Suguru Sasaki ,  Satoshi Machida ,  Takashi Taguchi

发明人： Suguru Sasaki ,  Satoshi Machida ,  Takashi Taguchi

IPC分类号： G02B5/18

CPC分类号： G02B5/1857 ,  G03F7/0005 ,  G03F7/0035

摘要： A method of forming a linear grating is disclosed. When forming a first resist pattern covering certain surface regions of a substrate, the mask pattern position is shifted and the first resist pattern is formed such that the trench in the target region is completely filled with the first resist pattern even when an error in positioning occurs. The surface of the first resist pattern is etched, and a lower resist pattern is left to the same level as the uppermost step of the silicon substrate. On top of this, an upper resist pattern having the same pattern as the first resist pattern is formed. At this time, the mask pattern position is shifted and the exposure dose is adjusted such that one edge of the upper resist pattern is positioned on the lower resist pattern, and the other edge is positioned in a prescribed region border portion. The lower resist pattern and upper resist pattern are used as a mask to etch the silicon substrate.

摘要翻译： 公开了一种形成线性光栅的方法。 当形成覆盖基板的某些表面区域的第一抗蚀剂图案时，掩模图案位置移动，并且形成第一抗蚀剂图案，使得即使当定位错误发生时，目标区域中的沟槽也完全被第一抗蚀剂图案填充 。 蚀刻第一抗蚀剂图案的表面，并且将下抗蚀剂图案保留到与硅衬底的最上层步骤相同的水平。 此外，形成具有与第一抗蚀剂图案相同的图案的上抗蚀剂图案。 此时，掩模图案位置移动，并且调整曝光剂量使得上抗蚀剂图案的一个边缘位于下抗蚀剂图案上，另一边缘位于规定区域边界部分中。 下抗蚀剂图案和上抗蚀剂图案用作掩模以蚀刻硅衬底。

公开(公告)号：US07721169B2

公开(公告)日：2010-05-18

申请号：US10367130

申请日：2003-02-14

申请人： Masahiro Yokomichi ,  Satoshi Machida ,  Yoshihiro Shibuya ,  Yukito Kawahara ,  Minoru Ariyama

发明人： Masahiro Yokomichi ,  Satoshi Machida ,  Yoshihiro Shibuya ,  Yukito Kawahara ,  Minoru Ariyama

IPC分类号： G01R31/28 ,  H04N1/46

CPC分类号： H04N5/3742 ,  G11C2029/3202 ,  H04N5/343

摘要： A scanning circuit has path switches connected between a plurality of data flip-flop circuits of the scanning circuit for sequentially reading an output signal in synchronism with a clock. A plurality of control signal lines select the path switches to arbitrarily skip reading of the flip-flop circuits that do not require the scanning circuit and always fix a potential of the skipped data flip-flop circuit. Only the arbitrary data is read, and in the case where unnecessary data exists, reading is skipped, to thereby increase the read rate.

摘要翻译： 扫描电路具有连接在扫描电路的多个数据触发器电路之间的路径开关，用于与时钟同步地顺序读取输出信号。 多个控制信号线选择路径切换以任意地跳过不需要扫描电路的触发电路的读取，并且始终固定跳过的数据触发器电路的电位。 仅读取任意数据，并且在存在不必要的数据的情况下，跳过读取，从而增加读取速率。

公开(公告)号：US07189953B2

公开(公告)日：2007-03-13

申请号：US10784494

申请日：2004-02-23

申请人： Satoshi Machida

发明人： Satoshi Machida

IPC分类号： H01L27/00

CPC分类号： H04N5/3653 ,  H01L27/146 ,  H04N5/3575 ,  H04N5/363 ,  H04N5/3658

摘要： A signal processing circuit has a sample/hold circuit for sampling an input signal comprised of a first signal and a second signal and for holding the first signal. The first signal comprises an optical signal obtained due to storage of electric charges generated due to light incident upon a photoelectric converter, and the second signal comprises a reference signal obtained due to resetting of the photoelectric converter. A subtracter receives an output signal of the sample/hold circuit and the input signal and obtains a difference between the output signal of the sample/hold circuit and the input signal. A voltage clamp circuit clamps a part or all of an output signal from the subtracter.

摘要翻译： 信号处理电路具有采样/保持电路，用于对由第一信号和第二信号组成的输入信号进行采样并保持第一信号。 第一信号包括由于存储由于光入射到光电转换器上的光产生的电荷而获得的光信号，并且第二信号包括由于光电转换器的复位而获得的参考信号。 减法器接收采样/保持电路的输出信号和输入信号，并获得采样/保持电路的输出信号与输入信号之间的差值。 电压钳位电路钳位来自减法器的一部分或全部输出信号。