公开(公告)号：US07863112B2

公开(公告)日：2011-01-04

申请号：US11970579

申请日：2008-01-08

Applicant: Deleep R. Nair ,  Terence B. Hook

Inventor： Deleep R. Nair ,  Terence B. Hook

IPC: H01L21/8283

CPC classification number: H01L27/0266 ,  H01L29/78

Abstract: Protecting a FET from plasma damage during FEOL processing by forming a FET-like structure in conjunction with and adjacent to an FET, in a same well as the FET, but having a body doped opposite to the well polarity. The FET-like structure is formed with thinner oxide than the gate oxide of the FET, has a gate structure (poly) connected with the gate of the FET, and may be shorted out by the first metal layer (M1).

Abstract translation: 通过在与FET相同的FET中与FET结合并与FET相邻并且具有与阱极性相反的掺杂体，在FEOL处理期间保护FET免受等离子体损伤。 FET型结构形成为具有比FET的栅极氧化物更薄的氧化物，具有与FET的栅极连接的栅极结构（poly），并且可以被第一金属层（M1）短路。

公开(公告)号：US07824933B2

公开(公告)日：2010-11-02

申请号：US10906826

申请日：2005-03-08

Applicant: Micah Galland ,  Terence B. Hook

Inventor： Micah Galland ,  Terence B. Hook

IPC: H01L21/66 ,  G01R31/26

CPC classification number: H01L22/14

Abstract: A process is provided for determining the effects of scattering from the edge of a resist during a doping process. Edges of a resist which has been patterned to create an n-well are simulated and individually stepped across a predetermined region in predetermined step sizes. The step sizes may vary from step to step after each step, the scattering effects due to the resist edge at its particular location is determined. A resist of virtually any shape may be divided into its component edges and each edge may be individually stepped during the process.

Abstract translation: 提供了一种用于在掺杂过程中确定来自抗蚀剂边缘的散射效应的过程。 已经图案化以形成n阱的抗蚀剂的边缘被模拟并以预定的步长单独地跨过预定区域。 步长可以在每个步骤之后逐步变化，确定由于其特定位置处的抗蚀剂边缘引起的散射效应。 实际上任何形状的抗蚀剂可以分成其部件边缘，并且每个边缘可以在该过程中单独地步进。

公开(公告)号：US20090258480A1

公开(公告)日：2009-10-15

申请号：US12101323

申请日：2008-04-11

Applicant: Terence B. Hook ,  Gerald Leake, JR.

Inventor： Terence B. Hook ,  Gerald Leake, JR.

IPC: H01L21/425

CPC classification number: H01L21/26586 ,  H01L21/26506 ,  H01L21/2652

Abstract: A first semiconductor region and a second semiconductor region separated by a shallow trench isolation region are formed in a semiconductor substrate. A photoresist is applied and patterned so that the first semiconductor region is exposed, while the second semiconductor region is covered. Depending on the setting of parameters for the location of an edge of the patterned photoresist, the slope of sidewalls of the photoresist, the thickness of the photoresist, and the direction of ion implantation, ions may, or may not, be implanted into the entirety of the surface portion of the first semiconductor region by shading or non-shading of the first semiconductor region. The semiconductor substrate may further comprise a third semiconductor region into which the dopants are implanted irrespective of the shading or non-shading of the first semiconductor region. The selection of shading or non-shading may be changed from substrate to substrate in manufacturing.

Abstract translation: 在半导体衬底中形成由浅沟槽隔离区隔开的第一半导体区域和第二半导体区域。 施加和图案化光致抗蚀剂，使得第一半导体区域被暴露，同时覆盖第二半导体区域。 取决于图案化光致抗蚀剂的边缘位置的参数的设置，光致抗蚀剂侧壁的斜率，光致抗蚀剂的厚度和离子注入的方向，离子可以或可以不植入整体 通过第一半导体区域的阴影或非阴影来形成第一半导体区域的表面部分。 半导体衬底还可以包括其中注入掺杂剂的第三半导体区域，而与第一半导体区域的阴影或非阴影无关。 阴影或非阴影的选择可以在制造过程中从衬底改变到衬底。

公开(公告)号：US20090179269A1

公开(公告)日：2009-07-16

申请号：US12317310

申请日：2008-12-22

Applicant: Terence B. Hook ,  Anda C. Mocuta ,  Jeffrey W. Sleight ,  Anthony K. Stamper

Inventor： Terence B. Hook ,  Anda C. Mocuta ,  Jeffrey W. Sleight ,  Anthony K. Stamper

IPC: H01L27/12

CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0251 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1207

Abstract: A chip can include a CMOS structure having a bulk device disposed in a first region of a semiconductor substrate in conductive communication with an underlying bulk region of the substrate, the first region and the bulk region having a first crystal orientation. An SOI device is disposed in a semiconductor-on-insulator (“SOI”) layer separated from the bulk region of the substrate by a buried dielectric layer, the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor (“PFET”) and the SOI device includes an n-type field effect transistor (“NFET”) device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor in conductive communication with a gate conductor of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region. The diodes are operable to conduct a discharge current to the bulk region when either a voltage on the gate conductor or a voltage on the source or drain region of the SOI device exceeds a diode's breakdown voltage.

Abstract translation: 芯片可以包括CMOS结构，其具有设置在半导体衬底的第一区域中的体器件，其与衬底的下面的体区域导电连通，第一区域和体区具有第一晶体取向。 SOI器件设置在绝缘体上半导体（“SOI”）层中，其通过掩埋电介质层与衬底的本体区域分离，SOI层具有与第一晶体取向不同的晶体取向。 在一个示例中，体器件包括p型场效应晶体管（“PFET”），并且SOI器件包括n型场效应晶体管（“NFET”）器件。 或者，体器件可以包括NFET，并且SOI器件可以包括PFET。 当SOI器件具有与本体器件的栅极导体导通的栅极导体时，除了存在与体区域反向偏置导电连通的二极管之外，SOI器件可能发生充电损坏。 当栅极导体上的电压或SOI器件的源极或漏极区域上的电压超过二极管的击穿电压时，二极管可操作以将放电电流传导到体区。

公开(公告)号：US07560345B2

公开(公告)日：2009-07-14

申请号：US11749775

申请日：2007-05-17

Applicant: Terence B. Hook ,  Jeffrey Scott Zimmerman

Inventor： Terence B. Hook ,  Jeffrey Scott Zimmerman

IPC: H01L21/336

CPC classification number: H01L27/0251 ,  G06F17/5045 ,  H01L21/84

Abstract: A method for preventing charging damage during manufacturing of an integrated circuit design, having silicon over insulator (SOI) transistors. The method prevents damage from charging during processing to the gate of IC devices by assigning regions to the IC design such that the devices located within the regions have electrically independent nets, identifying devices that may have a voltage differential between the source or drain, and gate as susceptible devices within a given region, and connecting a element across the respective source or drain, and the gate of each of the susceptible devices such that the element is positioned within the region. The method includes connecting compensating conductors to an element to eliminate potential charging damage.

Abstract translation: 一种用于在具有硅绝缘体（SOI）晶体管的集成电路设计的制造期间防止充电损坏的方法。 该方法通过向IC设计分配区域来防止在处理到IC器件的栅极期间的充电损坏，使得位于区域内的器件具有电独立的网络，识别可能在源极或漏极之间具有电压差的器件，以及栅极 作为给定区域内的易感设备，并且将元件连接在相应的源极或漏极以及每个敏感器件的栅极之间，使得元件位于该区域内。 该方法包括将补偿导体连接到元件以消除潜在的充电损坏。

公开(公告)号：US07300807B2

公开(公告)日：2007-11-27

申请号：US10709109

申请日：2004-04-14

Applicant: Douglas D Coolbaugh ,  Hayden C. Cranford, Jr. ,  Terence B. Hook ,  Anthony K. Stamper

Inventor： Douglas D Coolbaugh ,  Hayden C. Cranford, Jr. ,  Terence B. Hook ,  Anthony K. Stamper

IPC: H01L21/66

CPC classification number: H01L27/0802 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A circuit having a precision passive circuit element, such as a resistor or a capacitor, with a target value of an electrical parameter is fabricated on a substrate with a plurality of independent parallel-connected passive circuit elements. The plurality of passive circuit elements are designed to have a plurality of values of the electrical parameter which are spaced or offset at or around the target value of the electrical parameter, such as three circuit elements with one having a value at the target value, one having a value above the target value, and one having a value below the target value. Each passive circuit element also has a fuse in series therewith. A reference calibration structure is also fabricated, which can be a passive circuit element having the target value of the electrical parameter, in a reference area of the substrate under the same conditions and at the same time as fabrication of the plurality of passive circuit elements. The actual component value of the reference calibration structure is then measured, and based upon the measurement a single precision passive element of the plurality of parallel passive circuit elements is selected by blowing the fuses of, and thus deselecting, the other independent parallel connected passive circuit elements.

Abstract translation: 在具有多个独立并联无源电路元件的基板上制造具有目标值为电参数的精密无源电路元件（例如电阻器或电容器）的电路。 多个无源电路元件被设计为具有电参数的多个值，其在电参数的目标值处或周围被间隔或偏移，例如具有值在目标值的三个电路元件，一个 具有高于目标值的值，并且具有低于目标值的值。 每个无源电路元件还具有与其串联的保险丝。 还可以在相同条件下的基板的参考区域中以及在制造多个无源电路元件的同时，制造参考校准结构，其可以是具有电参数的目标值的无源电路元件。 然后测量参考校准结构的实际分量值，并且基于测量，多个并联无源电路元件中的单精度无源元件通过吹入另一个独立并联无源电路的熔丝并因此取消选择来选择 元素。

公开(公告)号：US20070271540A1

公开(公告)日：2007-11-22

申请号：US11383565

申请日：2006-05-16

Applicant: Chung-Ping Eng ,  Henry A. Bonges ,  Jeffrey S. Zimmerman ,  Terence B. Hook

Inventor： Chung-Ping Eng ,  Henry A. Bonges ,  Jeffrey S. Zimmerman ,  Terence B. Hook

IPC: G06F17/50

CPC classification number: G06F17/5063 ,  H01L27/0251

Abstract: Disclosed is a protection circuit for an integrated circuit device, wherein said protection circuit comprises: a first element connected to a gate of a first FET device; and a second element connected to a gate of a second FET device, wherein a drain/source of the first FET device and a drain/source of the second FET device are connected to a higher level connector and wherein the higher level connector eliminates a damaging current path between the first element and the second element.

Abstract translation: 公开了一种用于集成电路器件的保护电路，其中所述保护电路包括：连接到第一FET器件的栅极的第一元件; 以及连接到第二FET器件的栅极的第二元件，其中所述第一FET器件的漏极/源极和所述第二FET器件的漏极/源极连接到较高级别的连接器，并且其中所述较高级连接器消除了损坏 第一元件和第二元件之间的电流路径。

公开(公告)号：US07087470B2

公开(公告)日：2006-08-08

申请号：US10873012

申请日：2004-06-21

Applicant: Brent A. Anderson ,  Terence B. Hook

Inventor： Brent A. Anderson ,  Terence B. Hook

IPC: H01L29/72

CPC classification number: H01L21/823857

Abstract: A semiconductor device and a method of fabricating the semiconductor device, the semiconductor device including: one or more FETs of a first polarity and one or more FETs of a second and opposite polarity, at least one of the one or more FETs of the first polarity having a gate dielectric having a thickness different from a thickness of a gate dielectric of at least one of the one or more FETs of the second polarity.

Abstract translation: 一种半导体器件和半导体器件的制造方法，所述半导体器件包括：第一极性的一个或多个FET和具有第二极性和相反极性的一个或多个FET，所述一个或多个第一极性的FET中的至少一个 具有不同于所述第一极性的所述一个或多个FET中的至少一个的栅极电介质的厚度的栅极电介质。

公开(公告)号：US06700163B2

公开(公告)日：2004-03-02

申请号：US09683278

申请日：2001-12-07

Applicant: Matthew J. Breitwisch ,  Jeffrey S. Brown ,  Terence B. Hook ,  Randy W. Mann ,  Christopher S. Putnam ,  Mohammad I. Younus

Inventor： Matthew J. Breitwisch ,  Jeffrey S. Brown ,  Terence B. Hook ,  Randy W. Mann ,  Christopher S. Putnam ,  Mohammad I. Younus

IPC: H01L2976

CPC classification number: H01L21/823871 ,  H01L21/823842

Abstract: A selectively silicided semiconductor structure and a method for fabricating same is disclosed herein. The semiconductor structure has suicide present on the polysilicon line between the N+ diffusion or N+ active area and the P+ diffusion or active area at the N+/P+ junction of the polysilicon line, and silicide is not present on the N+ active area and the P+ active area. The presence of this selective silicidation creates a beneficial low-resistance connection between the N+ region of the polysilicon line and the P+ region of the polysilicon line. The absence of silicidation on the N+ and P+ active areas, specifically on the PFET and NFET structures, prevents current leakage associated with the silicidation of devices.

Abstract translation: 本文公开了选择性硅化半导体结构及其制造方法。 半导体结构在N +扩散或N +有源区域之间的多晶硅线路上存在自杀，并且在多晶硅线路的N + / P +结处的P +扩散或有源区域存在自杀，并且在N +有源区域和P +活性区域上不存在硅化物 区。 这种选择性硅化的存在在多晶硅线的N +区和多晶硅线的P +区之间产生有益的低电阻连接。 在N +和P +有源区，特别是PFET和NFET结构上不存在硅化，可防止与器件硅化相关的电流泄漏。

公开(公告)号：US06339018B1

公开(公告)日：2002-01-15

申请号：US09521719

申请日：2000-03-09

Applicant: Arne W. Ballantine ,  Terence B. Hook

Inventor： Arne W. Ballantine ,  Terence B. Hook

IPC: H01L213205

CPC classification number: H01L21/76897 ,  H01L29/665

Abstract: A method and structure for preventing device leakage. The method and structure includes forming a blocking layer of preferably nitride over a junction between a source/drain region and a shallow trench isolation. A silicide is then formed over a landed area of the source/drain region but is blocked by the blocking layer from forming over the junction between the source/drain region and the shallow trench isolation. This prevents device leakage at this location.

Abstract translation: 一种防止设备泄漏的方法和结构。 该方法和结构包括在源极/漏极区域和浅沟槽隔离之间的结上形成优选氮化物的阻挡层。 然后在源极/漏极区域的着陆区域上形成硅化物，但是被阻挡层阻挡在源极/漏极区域和浅沟槽隔离之间的结上形成。 这可以防止在此位置的设备泄漏。