公开(公告)号：US20240397833A1

公开(公告)日：2024-11-28

申请号：US18791412

申请日：2024-07-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chun-Hsien Lin

IPC: H10N50/80 ,  H10B61/00

Abstract: A semiconductor device for internet of things (IoT) device includes a substrate having an array region defined thereon and a ring of dummy pattern surrounding the array region. Preferably, the ring of dummy pattern includes a plurality of magnetic tunneling junctions (MTJs) and a ring of metal interconnect pattern overlapping the MTJs and surrounding the array region. The semiconductor device further includes a gap between the array region and the ring of dummy pattern.

公开(公告)号：US20240395929A1

公开(公告)日：2024-11-28

申请号：US18337396

申请日：2023-06-19

Applicant: United Microelectronics Corp.

Inventor： Chen-Yuan Lin ,  Yu-Cheng Lo ,  Tzu-Yun Chang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes a gate structure, a first doped region, a second doped region, an isolation structure, an insulating layer and a field plate. The gate structure is located on a substrate. The first doped region and the second doped region are located at two sides of the gate structure. The isolation structure is located in the substrate between the first doped region and the second doped region, and is separated from the gate structure by a non-zero distance. The insulating layer extends continuously from a portion of a top surface of the gate structure to a portion of a top surface of the isolation structure. The field plate is located on the insulating layer and has the same potential as the gate structure.

公开(公告)号：US20240395834A1

公开(公告)日：2024-11-28

申请号：US18795147

申请日：2024-08-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhaoyao Zhan ,  Qianwei DING ,  Xiaohong JIANG ,  Ching Hwa TEY

IPC: H01L27/146

Abstract: A photosensitive device includes an integrated circuit structure and a plurality of photodiodes disposed on the integrated circuit structure. The photodiodes respectively includes a first material layer and a second material layer overlapping on the first material layer and extending beyond the first material layer to directly contact a surface of the integrated circuit structure. The first material layer and the second material layer are made of two-dimensional semiconductor materials.

公开(公告)号：US20240393676A1

公开(公告)日：2024-11-28

申请号：US18334382

申请日：2023-06-14

Applicant: United Microelectronics Corp.

Inventor： Ming-Hsien Kuo ,  Chih-Hsien Tang ,  Song-Yi Lin

IPC: G03F1/70 ,  G06F30/398

Abstract: A design method of a photomask structure including the following steps is provided. A layout pattern is provided. The layout pattern includes first to third basic patterns. The second basic pattern is located between the first and third basic patterns and connected to the first and third basic patterns. There is a first jog portion between the first and second basic patterns, there is a second jog portion between the second and third basic patterns, and the first and second jog portions are located at two opposite sides of the layout pattern. The first and second jog portions are moved to align the first and second jog portions with each other and to eliminate the second basic pattern, wherein a first area change amount produced by moving the first jog portion is equal to a second area change amount produced by moving the second jog portion.

公开(公告)号：US12156487B2

公开(公告)日：2024-11-26

申请号：US18382055

申请日：2023-10-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu ,  Wang Xiang ,  Shen-De Wang

IPC: H10N70/00 ,  H10B63/00

Abstract: A RRAM (resistive random-access memory) device includes a bottom electrode line, a top electrode island and a resistive material. The bottom electrode line is directly on a first metal structure. The top electrode island is disposed beside the bottom electrode line. The resistive material is sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island. The present invention also provides a method of forming the RRAM device.

公开(公告)号：US12150315B2

公开(公告)日：2024-11-19

申请号：US18395649

申请日：2023-12-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Huei Tsai ,  Rai-Min Huang ,  Yu-Ping Wang ,  Hung-Yueh Chen

IPC: H10B61/00 ,  G11C11/16 ,  H01F10/32 ,  H01L23/528 ,  H10N50/80 ,  H10N50/85

Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.

公开(公告)号：US12150314B2

公开(公告)日：2024-11-19

申请号：US18512058

申请日：2023-11-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Te-Wei Yeh ,  Chien-Liang Wu

IPC: H10B61/00 ,  G11C7/18 ,  H10N50/80

Abstract: A magnetoresistive random access memory (MRAM) includes a first transistor and a second transistor on a substrate, a source line coupled to a first source/drain region of the first transistor, and a first metal interconnection coupled to a second source/drain region of the first transistor. Preferably, the first metal interconnection is extended to overlap the first transistor and the second transistor and the first metal interconnection further includes a first end coupled to the second source/drain region of the first transistor and a second end coupled to a magnetic tunneling junction (MTJ).

公开(公告)号：US12148809B2

公开(公告)日：2024-11-19

申请号：US17583225

申请日：2022-01-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chien-Hung Chen ,  Li-Ping Huang ,  Chun-Yen Tseng

IPC: H01L29/423 ,  G11C5/06 ,  G11C11/412 ,  H01L29/78 ,  H10B10/00

Abstract: The present invention provides a layout pattern of static random access memory, comprising a PU1 (first pull-up transistor), a PU2 (second pull-up transistor), a PD1A (first pull-down transistor), a PD1B (second pull-down transistor), a PD2A (third pull-down transistor), a PD2B (fourth pull-down transistor), a PG1A (first access transistor), a PG1B (second access transistor), a PG2A (third access transistor) and a PG2B (fourth access transistor) located on the substrate. The PD1A and the PD1B are connected in parallel with each other, the PD2A and the PD2B are connected in parallel with each other, wherein the gate structures include a first J-shaped gate structure, and the first J-shaped gate structure is an integrally formed structure.

公开(公告)号：US12148723B2

公开(公告)日：2024-11-19

申请号：US18077191

申请日：2022-12-07

Applicant: United Microelectronics Corp.

Inventor： Zhirui Sheng ,  Hui-Ling Chen ,  Chung-Hsing Kuo ,  Chun-Ting Yeh ,  Ming-Tse Lin ,  Chien En Hsu

IPC: H01L21/66 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: A structure of semiconductor device is provided, including a first circuit structure, formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure. One of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.

公开(公告)号：US20240379492A1

公开(公告)日：2024-11-14

申请号：US18780438

申请日：2024-07-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin

IPC: H01L23/367 ,  H01L21/768 ,  H01L23/00 ,  H01L23/373 ,  H01L23/48 ,  H01L23/485 ,  H01L25/00 ,  H01L25/07

Abstract: A semiconductor structure with a heat dissipation structure includes a first device wafer includes a front side and a back side. A first transistor is disposed on the front side. The first transistor includes a first gate structure disposed on the front side. Two first source/drain doping regions are embedded within the first device wafer at two side of the first gate structure. A channel region is disposed between the two first source/drain doping regions and embedded within the first device wafer. A first dummy metal structure contacts the back side of the first device wafer, and overlaps the channel region.