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    Method and apparatus for controlling cache line storage in cache memory
    44.
    发明授权
    Method and apparatus for controlling cache line storage in cache memory 有权

    公开(公告)号：US11636038B2

    公开(公告)日：2023-04-25

    申请号：US17575461

    申请日：2022-01-13

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： David A. Roberts

    IPC: G06F12/08 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/0815

    Abstract: A method and apparatus physically partitions clean and dirty cache lines into separate memory partitions, such as one or more banks, so that during low power operation, a cache memory controller reduces power consumption of the cache memory containing the clean only data. The cache memory controller controls refresh operation so that data refresh does not occur for clean data only banks or the refresh rate is reduced for clean data only banks. Partitions that store dirty data can also store clean data, however other partitions are designated for storing only clean data so that the partitions can have their refresh rate reduced or refresh stopped for periods of time. When multiple DRAM dies or packages are employed, the partition can occur on a die or package level as opposed to a bank level within a die.

    ASSIGNING VARIABLE LENGTH ADDRESS IDENTIFIERS TO PACKETS IN A PROCESSING SYSTEM
    45.
    发明申请
    ASSIGNING VARIABLE LENGTH ADDRESS IDENTIFIERS TO PACKETS IN A PROCESSING SYSTEM 有权

    公开(公告)号：US20220029954A1

    公开(公告)日：2022-01-27

    申请号：US17496256

    申请日：2021-10-07

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： David A. Roberts

    IPC: H04L29/12 ,  H04L12/741 ,  H04L12/753 ,  H04L29/06

    Abstract: A controller assigns variable length addresses to addressable elements that are connected to a network. The variable length addresses are determined based on probabilities that packets are addressed to the corresponding addressable element. The controller transmits, to the addressable elements via the network, a routing table indicating the variable length addresses assigned to the addressable elements. Routers or addressable elements receive the routing table and route one or more packets over the network to an addressable element using variable length addresses included in a header of the one or more packets.

    Memory object tagged memory monitoring method and system
    46.
    发明授权
    Memory object tagged memory monitoring method and system 有权

    公开(公告)号：US11061572B2

    公开(公告)日：2021-07-13

    申请号：US15136851

    申请日：2016-04-22

    Applicant: Advanced Micro Devices, Inc.

    Inventor： David A. Roberts ,  Michael Ignatowski

    IPC: G06F3/06 ,  G06F9/50 ,  G06F12/1027 ,  G06F12/1045

    Abstract: Described are a method and processing apparatus to tag and track objects related to memory allocation calls. An application or software adds a tag to a memory allocation call to enable object level tracking. An entry is made into an object tracking table, which stores the tag and a variety of statistics related to the object and associated memory devices. The object statistics may be queried by the application to tune power/performance characteristics either by the application making runtime placement decisions, or by off-line code tuning based on a previous run. The application may add a tag to a memory allocation call to specify the type of memory characteristics requested based on the object statistics.

    High performance context switching for virtualized FPGA accelerators
    47.
    发明授权
    High performance context switching for virtualized FPGA accelerators 有权

    公开(公告)号：US10540200B2

    公开(公告)日：2020-01-21

    申请号：US15809940

    申请日：2017-11-10

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Kevin Y. Cheng ,  David A. Roberts ,  William C. Brantley

    IPC: G06F9/46 ,  G06F9/50 ,  G06F13/40 ,  G06F13/42

    Abstract: A hardware context manager in a field-programmable gate array (FPGA) device includes configuration logic configured to program one or more programming regions in the FPGA device based on configuration data for implementing a target configuration of the one or more programming regions. Context management logic in the hardware context manager is coupled with the configuration logic and saves a first context corresponding to the target configuration by retrieving first state information from the set of one or more programming regions, where the first state information is generated based on the target configuration, and storing the retrieved first state information in a context memory. The context management logic restores the first context by transferring the first state information from the context memory to the one or more programming regions, and causing the configuration logic to program the one or more programming regions based on the configuration data.

    Network-aware cache coherence protocol enhancement
    48.
    发明授权
    Network-aware cache coherence protocol enhancement 有权

    公开(公告)号：US10402327B2

    公开(公告)日：2019-09-03

    申请号：US15358318

    申请日：2016-11-22

    Applicant: Advanced Micro Devices, Inc.

    Inventor： David A. Roberts ,  Ehsan Fatehi

    IPC: G06F12/08 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/0817 ,  G06F13/16

    Abstract: A non-uniform memory access system includes several nodes that each have one or more processors, caches, local main memory, and a local bus that connects a node's processor(s) to its memory. The nodes are coupled to one another over a collection of point-to-point interconnects, thereby permitting processors in one node to access data stored in another node. Memory access time for remote memory takes longer than local memory because remote memory accesses have to travel across a communications network to arrive at the requesting processor. In some embodiments, inter-cache and main-memory-to-cache latencies are measured to determine whether it would be more efficient to satisfy memory access requests using cached copies stored in caches of owning nodes or from main memory of home nodes.

    Logical memory address regions
    49.
    发明授权
    Logical memory address regions 有权

    公开(公告)号：US10255191B2

    公开(公告)日：2019-04-09

    申请号：US15133033

    申请日：2016-04-19

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Amin Farmahini-Farahani ,  David A. Roberts

    IPC: G06F12/00 ,  G06F12/1009 ,  G06F12/14 ,  G06F3/06 ,  G06F12/02

    Abstract: Systems, apparatuses, and methods for implementing logical memory address regions in a computing system. The physical memory address space of a computing system may be partitioned into a plurality of logical memory address regions. Each logical memory address region may be dynamically configured at run-time to meet changing application needs of the system. Each logical memory address region may also be configured separately from the other logical memory address regions. Each logical memory address region may have associated parameters that identify region start address, region size, cell-level mode, physical-to-device mapping scheme, address masks, access permissions, wear-leveling data, encryption settings, and compression settings. These parameters may be stored in a table which may be used when processing memory access requests.

    METHOD AND APPARATUS FOR PROVIDING WEAR LEVELING
    50.
    发明申请
    METHOD AND APPARATUS FOR PROVIDING WEAR LEVELING 审中-公开

    公开(公告)号：US20190051363A1

    公开(公告)日：2019-02-14

    申请号：US15857887

    申请日：2017-12-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Steven Raasch ,  Greg Sadowski ,  David A. Roberts

    IPC: G11C16/34 ,  G06F12/02 ,  G06F3/06

    Abstract: Exemplary embodiments provide wear spreading among die regions (i.e., one or more circuits) in an integrated circuit or among dies by using operating condition data in addition to or instead of environmental data such as temperature data, from each of a plurality of die regions. Control logic produces a cumulative amount of time each of the plurality of die regions has spent at an operating condition based on operating condition data wherein the operating condition data is based on at least one of the following operating characteristics: frequency of operation of the plurality of die regions, an operating voltage of the plurality of die regions, an activity level of the plurality of die regions, a timing margin of the plurality of die regions, and a number of detected faults of the plurality of die regions. The method and apparatus spreads wear among the plurality of same type of die regions by controlling task execution among the plurality of die regions using the die wear-out data.

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