公开(公告)号：US09965392B2

公开(公告)日：2018-05-08

申请号：US15246056

申请日：2016-08-24

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Anthony Asaro ,  Kevin Normoyle ,  Mark Hummel

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/0815 ,  G06F12/0806 ,  G06F12/0831 ,  G06F12/0846 ,  G06F12/0837 ,  G06F12/0804

CPC classification number: G06F12/0815 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0835 ,  G06F12/0837 ,  G06F12/0848 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/283 ,  G06F2212/608 ,  Y02D10/13

Abstract: Existing multiprocessor computing systems often have insufficient memory coherency and, consequently, are unable to efficiently utilize separate memory systems. Specifically, a CPU cannot effectively write to a block of memory and then have a GPU access that memory unless there is explicit synchronization. In addition, because the GPU is forced to statically split memory locations between itself and the CPU, existing multiprocessor computing systems are unable to efficiently utilize the separate memory systems. Embodiments described herein overcome these deficiencies by receiving a notification within the GPU that the CPU has finished processing data that is stored in coherent memory, and invalidating data in the CPU caches that the GPU has finished processing from the coherent memory. Embodiments described herein also include dynamically partitioning a GPU memory into coherent memory and local memory through use of a probe filter.

公开(公告)号：US20170301058A1

公开(公告)日：2017-10-19

申请号：US15638868

申请日：2017-06-30

Applicant: ATI Technologies ULC

Inventor： Milivoje Aleksic ,  Raymond M. Li ,  Danny H.M. Cheng ,  Carl K. Mizuyabu ,  Anthony Asaro

IPC: G06T1/60 ,  G06F13/16 ,  G06F13/28 ,  G06T1/20 ,  G09G5/39 ,  G09G5/393

CPC classification number: G06T1/60 ,  G06F13/1663 ,  G06F13/1684 ,  G06F13/28 ,  G06T1/20 ,  G09G5/39 ,  G09G5/393 ,  G09G2360/125

Abstract: An apparatus includes a unified system/graphics memory and a memory controller. The memory controller is operative to receive client data access requests associated with one or more clients and a central processing unit (CPU) data access request associated with a CPU, to a plurality of memory channels for accessing the unified system/graphics memory. The memory controller is operative to provide access to the plurality of memory channels, in parallel, by the CPU and at least one client of the one or more clients. The memory controller is operative to prioritize the CPU data access request to the unified memory over the client data access requests to the unified memory and control the plurality of memory channels to access, in parallel, data for the CPU and data for the at least one client based on a request of the client data access requests and the CPU data access request.

公开(公告)号：US09734549B2

公开(公告)日：2017-08-15

申请号：US14556801

申请日：2014-12-01

Applicant: ATI Technologies ULC

Inventor： Milivoje Aleksic ,  Raymond M. Li ,  Danny H. M. Cheng ,  Carl K. Mizuyabu ,  Anthony Asaro

IPC: G06F13/14 ,  G06T1/60 ,  G09G5/39 ,  G06F13/16 ,  G06F13/28 ,  G06T1/20 ,  G09G5/393

CPC classification number: G06T1/60 ,  G06F13/1663 ,  G06F13/1684 ,  G06F13/28 ,  G06T1/20 ,  G09G5/39 ,  G09G5/393 ,  G09G2360/125

Abstract: A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data.

公开(公告)号：US20170220485A1

公开(公告)日：2017-08-03

申请号：US15491616

申请日：2017-04-19

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Andrew G. KEGEL ,  Anthony Asaro

IPC: G06F12/1081 ,  G06F12/1009 ,  G06F12/1027

CPC classification number: G06F12/1081 ,  G06F12/02 ,  G06F12/1009 ,  G06F12/1027 ,  G06F13/28 ,  G06F2212/1016 ,  G06F2212/2532 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68

Abstract: A device may receive a direct memory access request that identifies a virtual address. The device may determine whether the virtual address is within a particular range of virtual addresses. The device may selectively perform a first action or a second action based on determining whether the virtual address is within the particular range of virtual addresses. The first action may include causing a first address translation algorithm to be performed to translate the virtual address to a physical address associated with a memory device when the virtual address is not within the particular range of virtual addresses. The second action may include causing a second address translation algorithm to be performed to translate the virtual address to the physical address when the virtual address is within the particular range of virtual addresses. The second address translation algorithm may be different from the first address translation algorithm.

公开(公告)号：US20170083240A1

公开(公告)日：2017-03-23

申请号：US14863026

申请日：2015-09-23

Applicant: Advanced Micro Devices, Inc. ,  ATI TECHNOLOGIES ULC

Inventor： Philip Rogers ,  Benjamin T. Sander ,  Anthony Asaro ,  Gongxian Jeffrey Cheng

IPC: G06F3/06 ,  G06F13/28 ,  G06F12/08

Abstract: A memory manager of a processor identifies a block of data for eviction from a first memory module to a second memory module. In response, the processor copies only those portions of the data block that have been identified as modified portions to the second memory module. The amount of data to be copied is thereby reduced, improving memory management efficiency and reducing processor power consumption.

公开(公告)号：US09201682B2

公开(公告)日：2015-12-01

申请号：US13923513

申请日：2013-06-21

Applicant: ATI Technologies ULC

Inventor： Gongxian Jeffrey Cheng ,  Anthony Asaro ,  Yinan Jiang

IPC: G06F11/00 ,  G06F9/00 ,  G06F9/455 ,  G06F1/24 ,  G06F11/14

CPC classification number: G06F9/45558 ,  G06F1/24 ,  G06F9/45533 ,  G06F11/1441 ,  G06F2009/4557 ,  G06F2009/45575 ,  G06F2009/45591

Abstract: In a hardware-based virtualization system, a hypervisor switches out of a first function into a second function. The first function is one of a physical function and a virtual function and the second function is one of a physical function and a virtual function. During the switching a malfunction of the first function is detected. The first function is reset without resetting the second function. The switching, detecting, and resetting operations are performed by a hypervisor of the hardware-based virtualization system. Embodiments further include a communication mechanism for the hypervisor to notify a driver of the function that was reset to enable the driver to restore the function without delay.

Abstract translation: 在基于硬件的虚拟化系统中，管理程序将第一个功能切换到第二个功能。 第一个功能是物理功能和虚拟功能之一，第二个功能是物理功能和虚拟功能之一。 在切换期间，检测到第一功能的故障。 第一个功能在不重置第二个功能的情况下被复位。 切换，检测和重置操作由基于硬件的虚拟化系统的管理程序执行。 实施例还包括用于管理程序的通信机制，以通知驾驶员已经重置的功能，以使得驾驶员能够无延迟地恢复功能。

公开(公告)号：US20250004949A1

公开(公告)日：2025-01-02

申请号：US18217291

申请日：2023-06-30

Applicant: Advanced Micro Devices, Inc ,  ATI Technologies ULC

Inventor： Paul Blinzer ,  Anthony Asaro ,  Nippon HarshadKumar Raval ,  Anthony Thomas Gutierrez ,  Leopold Grinberg ,  Millind Mittal ,  Samuel Richard Bayliss

IPC: G06F12/1009 ,  G06F12/14

Abstract: In accordance with the described techniques for extended attributes for shared page tables, a device includes an accelerator device and a memory management unit that maintains a first set of page tables and a second set of page tables. The second set of page tables includes extended attributes for accessing data that the accelerator device operates on. The memory management unit is configured to receive a virtual memory address, and translate the virtual memory address to a physical memory address using the first set of page tables. In addition, the memory management unit retrieves the extended attributes from the second set of page tables. In this way, data is accessed from the physical memory address based on the extended attributes.

公开(公告)号：US20240004562A1

公开(公告)日：2024-01-04

申请号：US17854903

申请日：2022-06-30

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Mark Fowler ,  Anthony Asaro ,  Vydhyanathan Kalyanasundharam

IPC: G06F3/06

CPC classification number: G06F3/0631 ,  G06F3/0679 ,  G06F3/0604

Abstract: A processing system including a parallel processing unit selectively allocating pages of memory for interleaving across configurable subsets of channels based on a mode of allocation. In some embodiments, in a first mode, a page of memory is allocated to and interleaved across a plurality of channels, and in a second mode, a page of memory is allocated to and interleaved across a subset of the plurality of channels.

公开(公告)号：US11675659B2

公开(公告)日：2023-06-13

申请号：US15375076

申请日：2016-12-09

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： James R. Magro ,  Ruihua Peng ,  Anthony Asaro ,  Kedarnath Balakrishnan ,  Scott P. Murphy ,  YuBin Yao

IPC: G06F11/10 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F11/1016 ,  G06F11/10 ,  G06F13/1626 ,  G06F13/4022

Abstract: In one form, a memory controller includes a command queue, an arbiter, and a replay queue. The command queue receives and stores memory access requests. The arbiter is coupled to the command queue for providing a sequence of memory commands to a memory channel. The replay queue stores the sequence of memory commands to the memory channel, and continues to store memory access commands that have not yet received responses from the memory channel. When a response indicates a completion of a corresponding memory command without any error, the replay queue removes the corresponding memory command without taking further action. When a response indicates a completion of the corresponding memory command with an error, the replay queue replays at least the corresponding memory command. In another form, a data processing system includes the memory controller, a memory accessing agent, and a memory system to which the memory controller is coupled.

公开(公告)号：US20230055695A1

公开(公告)日：2023-02-23

申请号：US18045128

申请日：2022-10-07

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Anirudh R. Acharya ,  Michael J. Mantor ,  Rex Eldon McCrary ,  Anthony Asaro ,  Jeffrey Gongxian Cheng ,  Mark Fowler

IPC: G06F9/48 ,  G06F9/52 ,  G06F9/54 ,  G06F12/1009 ,  G06F12/14 ,  G06T1/20

Abstract: Systems, apparatuses, and methods for abstracting tasks in virtual memory identifier (VMID) containers are disclosed. A processor coupled to a memory executes a plurality of concurrent tasks including a first task. Responsive to detecting one or more instructions of the first task which correspond to a first operation, the processor retrieves a first identifier (ID) which is used to uniquely identify the first task, wherein the first ID is transparent to the first task. Then, the processor maps the first ID to a second ID and/or a third ID. The processor completes the first operation by using the second ID and/or the third ID to identify the first task to at least a first data structure. In one implementation, the first operation is a memory access operation and the first data structure is a set of page tables. Also, in one implementation, the second ID identifies a first application of the first task and the third ID identifies a first operating system (OS) of the first task.