公开(公告)号：US20070020900A1

公开(公告)日：2007-01-25

申请号：US11175682

申请日：2005-07-06

申请人： Amitabh Jain

发明人： Amitabh Jain

IPC分类号： H01L21/3205

CPC分类号： H01L21/2807

摘要： The present invention provides, in one embodiment, a method for fabricating a microelectronic device. The method comprises implanting a dopant into a gate electrode located on a substrate. The gate electrode has a melting point below a melting point of the substrate. The method also comprises melting the gate electrode to allow the dopant to diffuse throughout the gate electrode. The method further comprises re-solidifying the gate electrode to increase dopant-occupied substitutional sites within the gate electrode.

摘要翻译： 在一个实施例中，本发明提供了一种用于制造微电子器件的方法。 该方法包括将掺杂剂注入到位于衬底上的栅电极中。 栅电极的熔点低于基板的熔点。 该方法还包括熔化栅电极以允许掺杂剂在整个栅电极中扩散。 该方法还包括重新固化栅电极以增加栅电极内的掺杂剂占据的取代位置。

公开(公告)号：US20060199346A1

公开(公告)日：2006-09-07

申请号：US11379426

申请日：2006-04-20

申请人： Amitabh Jain

发明人： Amitabh Jain

IPC分类号： H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for making a transistor within a semiconductor wafer. The method may include etching a recess at source/drain extension locations 90 and depositing SiGe within the recess to form SiGe source/drain extensions 90. Dopants are implanted into the SiGe source/drain extensions 90 and the semiconductor wafer 10 is annealed. Also, a transistor source/drain region 80, 90 having a SiGe source/drain extension 90 that contains evenly distributed dopants, is highly doped, and has highly abrupt edges.

摘要翻译： 一种在半导体晶片内制造晶体管的方法。 该方法可以包括蚀刻源极/漏极扩展位置90处的凹陷并在凹槽内沉积SiGe以形成SiGe源极/漏极延伸部90.掺杂剂注入到SiGe源极/漏极延伸部分90中并且半导体晶片10被退火。 此外，具有含有均匀分布的掺杂剂的SiGe源极/漏极延伸部90的晶体管源极/漏极区域80,90是高度掺杂的，并且具有高度突变的边缘。

公开(公告)号：US20060088969A1

公开(公告)日：2006-04-27

申请号：US10972872

申请日：2004-10-25

申请人： Amitabh Jain

发明人： Amitabh Jain

IPC分类号： H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/26506 ,  H01L21/268 ,  H01L29/6656 ,  H01L29/6659

摘要： Methods (70) are described for fabricating shallow and abrupt gradient drain extensions for MOS type transistors, in which a solid phase epitaxial recrystallization is performed within the drain extensions utilizing a laser SPER annealing process in the manufacture of semiconductor products. One method (70) includes a preamorphizing process (74) of implanting a heavy ion species such as Germanium deep into an extension region of a substrate adjacent a channel region of the substrate to form a deep amorphized region, then implanting boron or another such dopant species into an extension region of the substrate adjacent the channel region. The implanted dopant is then preannealed (78) at a low temperature to set the junction depth and doping concentration. The extensions and/or the deep source/drain regions are subsequently annealed (84) with a laser at a high temperature providing a solid phase epitaxial recrystallization in the regions proximate the channel region to achieve ultra high doping concentrations and activation levels with an abrupt gradient.

公开(公告)号：US07026218B2

公开(公告)日：2006-04-11

申请号：US10865342

申请日：2004-06-10

申请人： Antonio Luis Pacheco Rotondaro ,  James J. Chambers ,  Amitabh Jain

发明人： Antonio Luis Pacheco Rotondaro ,  James J. Chambers ,  Amitabh Jain

IPC分类号： H01L21/336

CPC分类号： H01L29/4925 ,  H01L21/28035 ,  H01L21/2807

摘要： The present invention pertains to formation of a PMOS transistor wherein a layer of silicon or SiGe inhibits p-type dopant from entering into an underlying gate dielectric layer. The p-type dopant can be added to a gate electrode material that overlies the silicon or SiGe layer and can diffuse down toward the silicon or SiGe layer. The layer of silicon or SiGe may be formed to a thickness of about 5 to 120 nanometers and doped with a dopant, such as indium (In), for example, to deter the p-type dopant from passing through the silicon or SiGe layer. The dopant may have a peak concentration within the layer of silicon or SiGe near the interface of the silicon or SiGe layer with the underlying layer of gate dielectric material. Allowing the gate electrode to be doped with the p-type dopant (e.g., boron) facilitates forming the transistor with an associated work function having a desired value (e.g., coincident with a Fermi level of about 4.8 to about 5.6 electron volts).

摘要翻译： 本发明涉及一种PMOS晶体管的形成，其中一层硅或SiGe抑制p型掺杂剂进入下面的栅介质层。 可以将p型掺杂剂添加到覆盖硅或SiGe层的栅电极材料中，并且可以向硅或SiGe层扩散。 硅或SiGe层可以形成为约5至120纳米的厚度，并掺杂有例如铟（In）的掺杂剂，以阻止p型掺杂剂通过硅或SiGe层。 掺杂剂可以在硅或SiGe层的界面附近与硅介电材料的下层之间的硅或SiGe层内具有峰值浓度。 允许栅电极掺杂有p型掺杂剂（例如硼）有助于以具有期望值（例如，与约4.8至约5.6电子伏特的费米能级一致）的相关功函数形成晶体管。

公开(公告)号：US20060073665A1

公开(公告)日：2006-04-06

申请号：US10955270

申请日：2004-09-30

申请人： Amitabh Jain

发明人： Amitabh Jain

IPC分类号： H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for making a transistor within a semiconductor wafer. The method may include etching a recess at source/drain extension locations 90 and depositing SiGe within the recess to form SiGe source/drain extensions 90. Dopants are implanted into the SiGe source/drain extensions 90 and the semiconductor wafer 10 is annealed. Also, a transistor source/drain region 80, 90 having a SiGe source/drain extension 90 that contains evenly distributed dopants, is highly doped, and has highly abrupt edges.

摘要翻译： 一种在半导体晶片内制造晶体管的方法。 该方法可以包括在源极/漏极扩展位置90处蚀刻凹陷并在凹槽内沉积SiGe以形成SiGe源极/漏极延伸部90。 将掺杂剂注入到SiGe源极/漏极延伸部分90中，并且半导体晶片10被退火。 此外，具有含有均匀分布的掺杂剂的SiGe源极/漏极延伸部90的晶体管源极/漏极区域80,90是高度掺杂的，并且具有高度突变的边缘。

公开(公告)号：US20060017079A1

公开(公告)日：2006-01-26

申请号：US10896421

申请日：2004-07-21

申请人： Srinivasan Chakravarthi ,  Amitabh Jain ,  Xin Zhang

发明人： Srinivasan Chakravarthi ,  Amitabh Jain ,  Xin Zhang

IPC分类号： H01L29/76 ,  H01L21/425 ,  H01L31/117 ,  H01L21/44

CPC分类号： H01L21/26513 ,  H01L21/02667 ,  H01L21/2022 ,  H01L21/26506 ,  H01L29/66575 ,  H01L29/78

摘要： We disclose a process for forming ultra shallow n+p junctions. The junction is formed by, for example, implanting 3E14 ions/cm2 of antimony ions at 5 keV into silicon. The silicon is pre-amorphized by a previous ion-implantation. The pre-amorphizing implant species may be germanium or arsenic. Germanium may be implanted at 15 keV and Arsenic may be implanted at 2 keV. Both the pre-amorphizing implant and the antimony implant are preferably through bare silicon surface—not covered with any foreign material with the exception of possibly a layer of native oxide. The junction is annealed at about 950° C. following the implants to re-crystallize the implanted region and to activate the implanted ions. The ultra shallow junction is superior because it has a abrupt junction, high sheet resistance and can be formed with low thermal budget.

摘要翻译： 我们公开了形成超浅层p + p结的方法。 该结通过例如以5keV将3E14离子/ cm 2的锑离子注入到硅中而形成。 硅通过先前的离子注入而被非晶化。 前非晶化植入物种可以是锗或砷。 锗可以以15keV注入，砷可以以2keV注入。 预非晶化植入物和锑植入物优选通过裸露的硅表面 - 未被任何异物覆盖，除了可能的一层天然氧化物之外。 接合点在大约950℃下退火，在植入物重新结晶植入区域并激活注入的离子之后。 超浅结是优越的，因为其具有突然的接合，高的薄层电阻，并且可以以低的热预算形成。

公开(公告)号：US20050059260A1

公开(公告)日：2005-03-17

申请号：US10810905

申请日：2004-03-26

申请人： Haowen Bu ,  Brian Hornung ,  P.R. Chidambaram ,  Amitabh Jain ,  Rajesh Khamankar ,  Nandu Mahalingam ,  Srinivansan Chakravarthi

发明人： Haowen Bu ,  Brian Hornung ,  P.R. Chidambaram ,  Amitabh Jain ,  Rajesh Khamankar ,  Nandu Mahalingam ,  Srinivansan Chakravarthi

IPC分类号： H01L21/00 ,  H01L21/265 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/336 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/08 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L21/26506 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/3185 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/0847 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845

摘要： The present invention teaches the formation of CMOS transistors using interfacial nitrogen at the interface between the lightly doped extension regions and an overlying insulating layer in combination with a capping layer of silicon nitride, both prior to the final source/drain anneal. Doses and energies may be increased for the P-channel lightly-doped drain, source and drain regions. The resulting transistors exhibit desirably high drive current and low off-state leakage current and overlap capacitance.

摘要翻译： 本发明教导了在最终的源极/漏极退火之前，在轻掺杂的延伸区域之间的界面处的界面氮和与氮化硅覆盖层结合的上覆绝缘层的CMOS晶体管的形成。 P沟道轻掺杂漏极，源极和漏极区域的剂量和能量可能会增加。 所得到的晶体管显示期望的高驱动电流和低截止状态的漏电流和重叠电容。

公开(公告)号：US06808997B2

公开(公告)日：2004-10-26

申请号：US10393749

申请日：2003-03-21

申请人： Amitabh Jain ,  Stephanie W. Butler

发明人： Amitabh Jain ,  Stephanie W. Butler

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/1083 ,  H01L29/7833

摘要： Methods are disclosed for forming ultra shallow junctions in semiconductor substrates using multiple ion implantation steps. The ion implantation steps include implantation of at least one electronically-active dopant as well as the implantation of at least two species effective at limiting junction broadening by channeling during dopant implantation and/or by thermal diffusion. Following dopant implantation, the electronically-active dopant is activated by thermal processing.

摘要翻译： 公开了使用多个离子注入步骤在半导体衬底中形成超浅结的方法。 离子注入步骤包括植入至少一种电子活性掺杂剂以及通过在掺杂剂注入期间通过沟槽化和/或通过热扩散来有效地限制结扩展的至少两种物质的注入。 在掺杂剂注入之后，电子活性掺杂剂通过热处理而被激活。

公开(公告)号：US08877581B2

公开(公告)日：2014-11-04

申请号：US12855736

申请日：2010-08-13

申请人： Amitabh Jain ,  Deborah J. Riley

发明人： Amitabh Jain ,  Deborah J. Riley

IPC分类号： H01L29/78 ,  H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L29/7848

摘要： An integrated circuit (IC) includes a plurality of strained metal oxide semiconductor (MOS) devices that include a semiconductor surface having a first doping type, a gate electrode stack over a portion of the semiconductor surface, and source/drain recesses that extend into the semiconductor surface and are framed by semiconductor surface interface regions on opposing sides of the gate stack. A first epitaxial strained alloy layer (rim) is on the semiconductor surface interface regions, and is doped with the first doping type. A second epitaxial strained alloy layer is on the rim and is doped with a second doping type that is opposite to the first doping type that is used to form source/drain regions.

摘要翻译： 集成电路（IC）包括多个应变金属氧化物半导体（MOS）器件，其包括具有第一掺杂类型的半导体表面，半导体表面的一部分上的栅极电极堆叠以及延伸到 半导体表面并且由栅堆叠的相对侧上的半导体表面界面区域构成。 第一外延应变合金层（边缘）在半导体表面界面区域上，并掺杂有第一掺杂型。 第二外延应变合金层位于边缘上并且掺杂有与用于形成源极/漏极区的第一掺杂类型相反的第二掺杂类型。

公开(公告)号：US08772118B2

公开(公告)日：2014-07-08

申请号：US13484592

申请日：2012-05-31

申请人： Amitabh Jain

发明人： Amitabh Jain

IPC分类号： H01L21/336 ,  H01L21/66

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L22/14 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process of integrated circuit manufacturing includes providing (32, 33) a spacer on a gate stack to provide a horizontal offset over the channel region for otherwise-direct application (34) of a PLDD implant dose in semiconductor, additionally depositing (35) a seal substance to provide a screen thickness vertically while thereby augmenting the spacer on the gate stack to provide an increased offset horizontally from the gate stack and form a horizontal screen free of etch, and subsequently providing (36) an NLDD implant dose for NLDD formation. Various integrated circuit structures, devices, and other processes of manufacture, and processes of testing are also disclosed.

摘要翻译： 集成电路制造的过程包括在栅极叠层上提供（32,33）间隔物，以在沟道区域上提供水平偏移，用于在半导体中另外存储（35）一个PLDD注入剂量的直接应用（34） 密封物质以垂直地提供屏幕厚度，从而增加栅极堆叠上的间隔物，以提供与栅极堆叠水平的增加的偏移，并形成没有蚀刻的水平屏幕，并随后提供（36）用于NLDD形成的NLDD注入剂量。 还公开了各种集成电路结构，装置和其它制造工艺以及测试过程。