公开(公告)号：US08001394B2

公开(公告)日：2011-08-16

申请号：US12023536

申请日：2008-01-31

申请人： Pradip Bose ,  Alper Buyuktosunoglu ,  Michael Stephen Floyd

发明人： Pradip Bose ,  Alper Buyuktosunoglu ,  Michael Stephen Floyd

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/3243 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171

摘要： A computer-implemented method and a system for managing power in a multi-core microprocessor are provided. A power management control microarchitecture in a chiplet translates a first command comprising a power setting. A chiplet comprises a processor core and associated memory cache. The power management control microarchitecture comprises power mode registers, power mode adjusters, translators, and microarchitectural power management techniques. The power management control microarchitecture sets microarchitectural power management techniques according to the power setting. The global power management controller issues the first command. The global power management controller may reside either on or off of the microprocessor. The global power management controller issues commands either directly for a specific chiplet out of the plurality of chiplets or to the plurality of chiplets and the control slave bus translates the command into sub-commands dedicated to specific chiplets within the plurality of chiplets. Each chiplet may be set to separate power levels.

摘要翻译： 提供了一种计算机实现的方法和用于管理多核微处理器中的电力的系统。 小电流中的电源管理控制微体系结构转换包括功率设置的第一命令。 小巧包括处理器核心和相关联的存储器高速缓存。 功率管理控制微体系结构包括功率模式寄存器，功率模式调节器，转换器和微架构电源管理技术。 电源管理控制微架构根据功率设置设置微体系结构电源管理技术。 全球电源管理控制器发出第一个命令。 全局功率管理控制器可以驻留在微处理器上或者关闭。 全局功率管理控制器直接针对多个小芯片中的特定小时或多个小芯片发出命令，并且控制从总线将命令转换为专用于多个小芯片内的特定小芯片的子命令。 每个小穗可以设置为分开的功率水平。

公开(公告)号：US07996703B2

公开(公告)日：2011-08-09

申请号：US12023550

申请日：2008-01-31

申请人： Michael Stephen Floyd ,  Norman Karl James ,  Jeffrey William Kellington ,  Larry S. Leitner

发明人： Michael Stephen Floyd ,  Norman Karl James ,  Jeffrey William Kellington ,  Larry S. Leitner

IPC分类号： G06F1/04 ,  G06F1/14

CPC分类号： G06F9/4403 ,  G06F1/24 ,  G06F1/3203

摘要： Exemplary embodiments provide a computer-implemented method and a system for a startup cycle for a cycle deterministic start. An initializing mechanism applies power to a microprocessor. The initializing mechanism initializes the configuration of the microprocessor. The initializing mechanism initializes a timer. The initializing mechanism then sends a clock start command to the microprocessor. The clocks on the microprocessor are started. Upon the clocks starting, the timer begins and allows temporary transients, such as voltage droop due to a large instantaneous change in demand for current due to the commencement of clock switching. Responsive to the timer reaching a target value, an interrupt unit sends a system reset interrupt. Responsive to the interrupt unit sending the system reset interrupt, an instruction fetch unit fetches a first instruction. This operation will be deterministic to the state of the rest of the microprocessor memory elements (latches, arrays, et al.).

摘要翻译： 示例性实施例提供计算机实现的方法和用于循环确定性开始的启动周期的系统。 初始化机制向微处理器施加电力。 初始化机制初始化微处理器的配置。 初始化机制初始化一个定时器。 初始化机制然后向微处理器发送时钟启动命令。 微处理器上的时钟启动。 在时钟启动时，定时器开始并允许临时瞬变，例如由于时钟切换开始时对电流的需求的大的瞬间变化而导致的电压下降。 响应于定时器达到目标值，中断单元发送系统复位中断。 响应于中断单元发送系统复位中断，指令提取单元获取第一条指令。 该操作对于微处理器存储元件（锁存器，阵列等）的其余部分的状态将是确定的。

公开(公告)号：US07962887B2

公开(公告)日：2011-06-14

申请号：US12139928

申请日：2008-06-16

申请人： Carl John Anderson ,  Michael Stephen Floyd ,  Norman Karl James ,  Phillip John Restle

发明人： Carl John Anderson ,  Michael Stephen Floyd ,  Norman Karl James ,  Phillip John Restle

IPC分类号： G06F17/50 ,  G06F11/22 ,  G05B13/02

CPC分类号： G05B19/0428 ,  G05B2219/23399 ,  G05B2219/25064

摘要： Sensors on the integrated circuit are used to detect the current operating state of the chip, such as frequency, voltage, temperature characteristics, or variation in the integrated circuit manufacturing process. In response, the integrated circuit may choose to modify operational parameters (such as frequency, voltage, or power-down states) in order to dynamically and autonomously maintain an optimal performance and/or power-efficiency operational point.

摘要翻译： 集成电路中的传感器用于检测芯片的当前工作状态，例如频率，电压，温度特性或集成电路制造过程中的变化。 作为响应，集成电路可以选择修改操作参数（例如频率，电压或掉电状态），以便动态地和自主地维持最佳性能和/或功率效率操作点。

公开(公告)号：US20100268975A1

公开(公告)日：2010-10-21

申请号：US12424161

申请日：2009-04-15

申请人： Pradip Bose ,  Alper Buyuktosunoglu ,  Michael Stephen Floyd

发明人： Pradip Bose ,  Alper Buyuktosunoglu ,  Michael Stephen Floyd

IPC分类号： G06F1/26

CPC分类号： G06F11/348 ,  G06F11/3006 ,  G06F11/3024 ,  G06F11/3062 ,  G06F2201/88 ,  Y02D10/34

摘要： A method for estimating power consumption within a multi-core microprocessor chip is provided. An authorized user selects a set of activities to be monitored. A value for each activity of the set of activities is stored in a separate counter of a set of counters, forming a set of stored values. The value comprises the count multiplied by a weight factor specific to the activity. The set of activities are grouped into subsets. The stored values corresponding to each activity in each subset are summed, forming a total value for each subset. The total value of each subset is multiplied by a factor corresponding to the subset, forming a scaled value for each subset. The scaled value of each subset is summed, forming a power usage value. A power manager adjusts the operational parameters of the unit based on a comparison of the power usage value to a threshold value.

摘要翻译： 提供了一种用于估计多核微处理器芯片内的功耗的方法。 授权用户选择要监视的一组活动。 一组活动的每个活动的值存储在一组计数器的单独计数器中，形成一组存储的值。 该值包括计数乘以活动特有的权重因子。 该组活动被分组成子集。 将对应于每个子集中的每个活动的存储值相加，形成每个子集的总值。 每个子集的总值乘以与子集对应的因子，形成每个子集的缩放值。 将每个子集的缩放值相加，形成功率使用值。 功率管理器基于功率使用值与阈值的比较来调整单元的操作参数。

公开(公告)号：US20100262808A1

公开(公告)日：2010-10-14

申请号：US12420143

申请日：2009-04-08

申请人： Pradip Bose ,  Alper Buyuktosunoglu ,  Michael Stephen Floyd ,  Dung Quoc Nguyen ,  Bruce Joseph Ronchetti

发明人： Pradip Bose ,  Alper Buyuktosunoglu ,  Michael Stephen Floyd ,  Dung Quoc Nguyen ,  Bruce Joseph Ronchetti

IPC分类号： G06F9/30

CPC分类号： G06F9/3861 ,  G06F9/3824 ,  G06F9/3836 ,  G06F11/348 ,  G06F2201/88 ,  Y02D10/34

摘要： The illustrative embodiments described herein provide a computer-implemented method, apparatus, and a system for managing instructions. A load/store unit receives a first instruction at a port. The load/store unit rejects the first instruction in response to determining that the first instruction has a first reject condition. Then, the instruction sequencing unit activates a first bit in response to the load/store unit rejection the first instruction. The instruction sequencing unit blocks the first instruction from reissue while the first bit is activated. The processor unit determines a class of rejection of the first instruction. The instruction sequencing unit starts a timer. The length of the timer is based on the class of rejection of the first instruction. The instruction sequencing unit resets the first bit in response to the timer expiring. The instruction sequencing unit allows the first instruction to become eligible for reissue in response to resetting the first bit.

摘要翻译： 本文描述的说明性实施例提供了一种计算机实现的方法，装置和用于管理指令的系统。 加载/存储单元在端口接收第一条指令。 响应于确定第一指令具有第一拒绝条件，加载/存储单元拒绝第一指令。 然后，指令排序单元响应于加载/存储单元来激活第一位以拒绝第一指令。 当第一位被激活时，指令排序单元阻止重新发行的第一条指令。 处理器单元确定第一指令的拒绝类。 指令排序单元启动定时器。 定时器的长度取决于第一条指令的拒绝类型。 指令排序单元重置响应定时器超时的第一位。 响应于重置第一位，指令排序单元允许第一指令变得有资格重新发行。

公开(公告)号：US20100125436A1

公开(公告)日：2010-05-20

申请号：US12274534

申请日：2008-11-20

申请人： Harold W. Chase ,  Soraya Ghiasi ,  Michael Stephen Floyd ,  Joshua David Friedrich ,  Steven Paul Hartman ,  Norman Karl James ,  Malcolm Scott Ware ,  Richard L. Willaman

发明人： Harold W. Chase ,  Soraya Ghiasi ,  Michael Stephen Floyd ,  Joshua David Friedrich ,  Steven Paul Hartman ,  Norman Karl James ,  Malcolm Scott Ware ,  Richard L. Willaman

IPC分类号： G06F15/00

CPC分类号： G06F11/24

摘要： A benchmark tester retrieves a voltage margin that corresponds to a device that a system includes. The voltage margin indicates an additional amount of voltage to apply to a nominal voltage that, when added, results in the device operating at a power limit while executing a worst-case power workload. Next, the benchmark tester (or thermal power management device) sets an input voltage for the device to a value equal to the sum of the voltage margin and the nominal voltage. The benchmark tester then dynamically benchmark tests the system, which includes adjusting the device's frequency and input voltage while ensuring that the device does not exceed the device's power limit. In turn, the benchmark tester records a guaranteed minimum performance boost for the system based upon a result of the benchmark testing.

摘要翻译： 基准测试仪检索与系统包括的设备相对应的电压裕度。 电压裕度表示额外的电压值，以适用于额定电压，当加入时，会导致器件在执行最坏情况下的工作负载时工作在功率极限。 接下来，基准测试器（或热功率管理器件）将器件的输入电压设置为等于电压裕度和额定电压之和的值。 基准测试仪然后动态基准测试系统，包括调整设备的频率和输入电压，同时确保设备不超过设备的功率限制。 反过来，基准测试人员会根据基准测试的结果记录系统的最低性能保证。

公开(公告)号：US07418629B2

公开(公告)日：2008-08-26

申请号：US11055870

申请日：2005-02-11

申请人： Ra'ed Mohammad Al-Omari ,  Michael Stephen Floyd ,  Paul Frank Lecocq

发明人： Ra'ed Mohammad Al-Omari ,  Michael Stephen Floyd ,  Paul Frank Lecocq

IPC分类号： G06F11/00

CPC分类号： G06F11/2268 ,  G06F11/348

摘要： A method, apparatus, and computer program product are disclosed in a data processing system for synchronizing the triggering of multiple hardware trace facilities using an existing bus. The multiple hardware trace facilities include a first hardware trace facility and a second hardware trace facility. The data processing system includes a first processor that includes the first hardware trace facility and first processing units that are coupled together utilizing the system bus, and a second processor that includes the second hardware trace facility and second processing units that are coupled together utilizing the system bus. Information is transmitted among the first and second processing units utilizing the system bus when the processors are in a normal, non-tracing mode, where the information is formatted according to a standard system bus protocol. Trigger events are transmitted to the hardware trace facilities utilizing the same standard system bus, where the trigger events are also formatted according to the standard system bus protocol.

摘要翻译： 在用于使用现有总线触发多个硬件跟踪设备的数据处理系统中公开了一种方法，装置和计算机程序产品。 多个硬件跟踪设备包括第一个硬件跟踪设备和第二个硬件跟踪设备。 数据处理系统包括第一处理器，其包括第一硬件跟踪设备和利用系统总线耦合在一起的第一处理单元，以及包括第二硬件跟踪设备的第二处理器和利用系统耦合在一起的第二处理单元 总线。 当处理器处于正常的非跟踪模式时，利用系统总线在第一和第二处理单元之间传送信息，其中信息根据标准系统总线协议被格式化。 触发事件使用相同的标准系统总线传输到硬件跟踪设备，触发事件也根据标准系统总线协议进行格式化。

公开(公告)号：US07155600B2

公开(公告)日：2006-12-26

申请号：US10422648

申请日：2003-04-24

申请人： William Elton Burky ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Balaram Sinharoy

发明人： William Elton Burky ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Balaram Sinharoy

IPC分类号： G06F15/00 ,  G06F15/76 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44

CPC分类号： G06F9/485

摘要： A method and logical apparatus for switching between single-threaded and multi-threaded execution states within a simultaneous multi-threaded (SMT) processor provides a mechanism for switching between single-threaded and multi-threaded execution. The processor receives an instruction specifying a transition from a single-threaded to a multi-threaded mode or vice-versa and halts execution of all threads executing on the processor. Internal control logic controls a sequence of events that ends instruction prefetching, dispatch of new instructions, interrupt processing and maintenance operations and waits for operation of the processor to complete for instructions that are in process. Then, the logic determines one or more threads to start in conformity with a thread enable state specifying the enable state of multiple threads and reallocates various resources, dividing them between threads if multiple threads are specified for further execution (multi-threaded mode) or allocating substantially all of the resources to a single thread if further execution is specified as single-threaded mode. The processor then starts execution of the remaining enabled threads.

摘要翻译： 用于在同时多线程（SMT）处理器中的单线程和多线程执行状态之间切换的方法和逻辑设备提供了在单线程和多线程执行之间进行切换的机制。 处理器接收指定从单线程转换到多线程模式或反之亦然的指令，并停止在处理器上执行的所有线程的执行。 内部控制逻辑控制结束指令预取，调度新指令，中断处理和维护操作的事件序列，并等待处理器的操作完成以处理正在进行的指令。 然后，逻辑根据指定多个线程的使能状态的线程使能状态确定一个或多个线程，以重新分配各种资源，如果多个线程被指定用于进一步执行（多线程模式）或分配 如果进一步执行被指定为单线程模式，则基本上所有的资源到单个线程。 然后，处理器开始执行剩余的已启用线程。

公开(公告)号：US07117126B2

公开(公告)日：2006-10-03

申请号：US09946217

申请日：2001-09-05

申请人： Michael Stephen Floyd ,  Ravi Kumar Arimilli ,  Daniel Mark Dreps ,  Frank David Ferraiolo ,  Kevin F. Reick

发明人： Michael Stephen Floyd ,  Ravi Kumar Arimilli ,  Daniel Mark Dreps ,  Frank David Ferraiolo ,  Kevin F. Reick

IPC分类号： G06F11/30

CPC分类号： H04L7/02 ,  H04L1/24 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/005

摘要： A data processing system includes a mechanism to periodically idle the normal system operation to allow recalibration of its interface circuitry by transmission of data with transitions and logic levels indicative of actual operation. Provision is made to protect actual data of the system from corruption during recalibration.

公开(公告)号：US07080288B2

公开(公告)日：2006-07-18

申请号：US10425423

申请日：2003-04-28

申请人： Frank David Ferraiolo ,  Michael Stephen Floyd ,  Robert James Reese ,  Kevin Franklin Reick

发明人： Frank David Ferraiolo ,  Michael Stephen Floyd ,  Robert James Reese ,  Kevin Franklin Reick

IPC分类号： G06F11/22

CPC分类号： H04L43/50 ,  G06F11/221 ,  H04L1/00 ,  H04L1/242

摘要： A method an apparatus for interface failure survivability using error correction provides operation of an interface when a number of bits of the interface less than or equal to available error correction depth are present. Initialization tests are used to determine whether the interface errors due to failed interconnects or circuits can be corrected, or whether the interface must be disabled. Subsequent alignment at initialization or during operation idle periods may be disabled for any failed bit paths. The failed bit path indications are determined and maintained in hardware, and used to bypass subsequent calibrations that could otherwise corrupt the interface. A fault indication specifying total failure may be generated and used to shut down the interface and/or connected subsystem in response to an uncorrectable condition and request immediate repair. A second fault indication specifying correctable failure may be generated and used to indicate a need for eventual repair.

摘要翻译： 一种使用错误校正的接口故障生存性的装置的方法提供当接口的位数小于或等于可用纠错深度时的接口的操作。 初始化测试用于确定由于互连或电路故障导致的接口错误是否可以更正，还是禁用接口。 对于任何故障的位路径，在初始化或操作空闲期间的后续对齐可被禁用。 失败的位路径指示被确定并维护在硬件中，并用于绕过可能会破坏接口的后续校准。 可以产生指示全部故障的故障指示并用于响应于不可校正的状况而关闭接口和/或连接的子系统并请求立即修复。 可以产生指示可修正故障的第二故障指示并用于指示最终修复的需要。