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41.发明授权Integration of high-k metal gate stack into direct silicon bonding (DSB) hybrid orientation technology (HOT) pMOS process flow 有权将高k金属栅极堆叠集成到直接硅键（DSB）混合取向技术（HOT）pMOS工艺流程中公开(公告)号：US07943479B2
公开(公告)日：2011-05-17
申请号：US12193956
申请日：2008-08-19
IPC分类号： H01L21/76
CPC分类号： H01L29/045 , H01L21/26506 , H01L21/28088 , H01L21/28202 , H01L21/823807 , H01L21/823828 , H01L29/4966 , H01L29/517
摘要： A method for semiconductor processing provides a DSB semiconductor body having a first crystal orientation layer, and a second crystal orientation layer, and a border region disposed between the first and second crystal orientations. A high-k metal gate stack is deposited over the first crystal orientation layer that comprises an insulation layer, a high-k dielectric layer, a first metal layer, and a second metal layer thereon.
摘要翻译： 一种用于半导体处理的方法提供了具有第一晶体取向层和第二晶体取向层的DSB半导体本体，以及设置在第一和第二晶体取向之间的边界区域。 在第一晶体取向层上沉积高k金属栅极堆叠，其上包括绝缘层，高k电介质层，第一金属层和第二金属层。
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公开(公告)号：US20110111553A1
公开(公告)日：2011-05-12
申请号：US13006224
申请日：2011-01-13
IPC分类号： H01L51/40
CPC分类号： H01L29/66659 , H01L21/26506 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/823892 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/36 , H01L29/78612 , H01L29/78654
摘要： The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).
摘要翻译： 本发明是一种用于在MOS晶体管结构中形成超陡掺杂分布的方法。 该方法包括在栅极电介质（50）下面形成含碳层（110），并在MOS晶体管的源极和漏极区域（80）形成。 含碳层（110）将防止掺杂剂扩散到栅极电介质层（50）正下方的区域（40）中。
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43.发明授权Method of making (100) NMOS and (110) PMOS sidewall surface on the same fin orientation for multiple gate MOSFET with DSB substrate 有权制造具有DSB衬底的多栅极MOSFET的（100）NMOS和（110）PMOS侧壁表面的方法公开(公告)号：US07897994B2
公开(公告)日：2011-03-01
申请号：US11764442
申请日：2007-06-18
申请人： Weize Xiong , Cloves Rinn Cleavelin , Angelo Pinto , Rick L. Wise
发明人： Weize Xiong , Cloves Rinn Cleavelin , Angelo Pinto , Rick L. Wise
IPC分类号： H01L29/66
CPC分类号： H01L27/0886 , G11C11/412 , H01L21/823807 , H01L21/823821 , H01L27/0207 , H01L27/092 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/045 , Y10S257/90 , Y10S438/973 , Y10S438/982
摘要： A method of forming an integrated circuit device that includes a plurality of MuGFETs is disclosed. A PMOS fin of a MuGFET is formed on a substrate. The PMOS fin includes a channel of a first surface of a first crystal orientation. A NMOS fin of another MuGFET is formed on the substrate. The NMOS fin includes a channel on the substrate at one of 0° and 90° to the PMOS fin and includes a second surface of a second crystal orientation.
摘要翻译： 公开了一种形成包括多个MuGFET的集成电路器件的方法。 在基板上形成MuGFET的PMOS鳍。 PMOS鳍包括第一晶体取向的第一表面的沟道。 在基板上形成另一个MuGFET的NMOS鳍。 所述NMOS鳍片包括在所述衬底上与所述PMOS鳍片0°和90°之一处的通道，并且包括第二晶体取向的第二表面。
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公开(公告)号：US07883977B2
公开(公告)日：2011-02-08
申请号：US12356371
申请日：2009-01-20
IPC分类号： H01L21/336
CPC分类号： H01L29/66659 , H01L21/26506 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/823892 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/36 , H01L29/78612 , H01L29/78654
摘要： The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).
摘要翻译： 本发明是一种用于在MOS晶体管结构中形成超陡掺杂分布的方法。 该方法包括在栅极电介质（50）下面形成含碳层（110），并在MOS晶体管的源极和漏极区域（80）形成。 含碳层（110）将防止掺杂剂扩散到栅极电介质层（50）正下方的区域（40）中。
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45.发明申请公开(公告)号：US20100279481A1
公开(公告)日：2010-11-04
申请号：US12627794
申请日：2009-11-30
申请人： Jeffrey A. Babcock , Angelo Pinto , Manfred Schiekofer , Scott G. Balster , Gregory E. Howard , Alfred Hausler
发明人： Jeffrey A. Babcock , Angelo Pinto , Manfred Schiekofer , Scott G. Balster , Gregory E. Howard , Alfred Hausler
IPC分类号： H01L21/331
CPC分类号： H01L29/66265 , H01L21/82285 , H01L29/66242 , H01L29/7317 , H01L29/7378
摘要： An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors (30, 50, 60), each having a buried collector region (26′). A carbon-bearing diffusion barrier (28c) is disposed over the buried collector region (26′), to inhibit the diffusion of dopant from the buried collector region (26′) into the overlying epitaxial layer (28). The diffusion barrier (28c) may be formed by incorporating a carbon source into the epitaxial formation of the overlying layer (28), or by ion implantation. In the case of ion implantation of carbon or SiGeC, masks (52, 62) may be used to define the locations of the buried collector regions (26′) that are to receive the carbon; for example, portions underlying eventual collector contacts (33, 44c) may be masked from the carbon implant so that dopant from the buried collector region (26′) can diffuse upward to meet the contact (33). MOS transistors (70, 80) including the diffusion barrier (28) are also disclosed.
摘要翻译： 公开了一种集成电路及其制造方法。 集成电路包括垂直双极晶体管（30,50,60），每个具有一个埋设集电极区域（26'）。 含碳扩散阻挡层（28c）设置在掩埋集电极区域（26'）之上，以阻止掺杂剂从掩埋的集电极区域（26'）扩散到上覆的外延层（28）中。 扩散阻挡层（28c）可以通过将碳源引入上覆层（28）的外延层中，或通过离子注入形成。 在碳或SiGeC的离子注入的情况下，可以使用掩模（52,62）来限定待接收碳的掩埋收集器区域（26'）的位置; 例如，最终的集电极触点（33,44c）下面的部分可以从碳注入掩模，使得来自掩埋的集电极区域（26'）的掺杂剂可向上扩散以满足触点（33）。 还公开了包括扩散阻挡层（28）的MOS晶体管（70,80）。
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46.发明申请USE OF IN-SITU HCL ETCH TO ELIMINATE BY OXIDATION RECRYSTALLIZATION BORDER DEFECTS GENERATED DURING SOLID PHASE EPITAXY (SPE) IN THE FABRICATION OF NANO-SCALE CMOS TRANSISTORS USING DIRECT SILICON BOND SUBSTRATE (DSB) AND HYBRID ORIENTATION TECHNOLOGY (HOT) 有权通过使用直接硅胶基板（DSB）和混合方向技术（HOT）在纳米尺寸CMOS晶体管的制造过程中，通过氧化重结晶边界产生的边界缺陷来消除现场HCL蚀刻的使用。公开(公告)号：US20100216286A1
公开(公告)日：2010-08-26
申请号：US12391657
申请日：2009-02-24
申请人： Angelo Pinto
发明人： Angelo Pinto
IPC分类号： H01L21/302 , H01L21/31 , H01L21/8238
CPC分类号： H01L21/823412 , H01L21/02381 , H01L21/02433 , H01L21/02609 , H01L21/02667 , H01L21/823807
摘要： A method for reducing defects at an interface between a amorphized, recrystallized cleaved wafer layer and an unamorphized cleaved wafer layer can comprise an anneal and an exposure to hydrochloric acid. The anneal and acid exposure can be performed within an epitaxial reactor chamber to minimize wafer transport.
摘要翻译： 用于减少非晶化，再结晶的切割的晶片层和未变形的切割的晶片层之间的界面处的缺陷的方法可以包括退火和暴露于盐酸。 退火和酸暴露可以在外延反应器室内进行以最小化晶片输送。
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47.发明授权Semiconductor device made by the method of producing hybrid orientnation (100) strained silicon with (110) silicon 有权通过制造具有（110）硅的杂化取向（100）应变硅的方法制造的半导体器件公开(公告)号：US07767510B2
公开(公告)日：2010-08-03
申请号：US11760822
申请日：2007-06-11
申请人： Rick L. Wise , Angelo Pinto
发明人： Rick L. Wise , Angelo Pinto
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/324 , H01L21/76254 , H01L29/045 , H01L29/665
摘要： There is provided a method of manufacturing a semiconductor device. In one aspect, the method includes providing a strained silicon layer having a crystal orientation located over a semiconductor substrate having a different crystal orientation. A mask is placed over a portion of the strained silicon layer to leave an exposed portion of the strained silicon layer. The exposed portion of the strained silicon layer is amorphized and re-crystallized to a crystal structure having an orientation the same as the semiconductor substrate.
摘要翻译： 提供了制造半导体器件的方法。 一方面，该方法包括提供具有位于具有不同晶体取向的半导体衬底之上的晶体取向的应变硅层。 将掩模放置在应变硅层的一部分上以留下应变硅层的暴露部分。 应变硅层的暴露部分非晶化并再结晶成具有与半导体衬底相同的取向的晶体结构。
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公开(公告)号：US20080132012A1
公开(公告)日：2008-06-05
申请号：US11928652
申请日：2007-10-30
IPC分类号： H01L21/8238
CPC分类号： H01L29/66659 , H01L21/26506 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/823892 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/36 , H01L29/78612 , H01L29/78654
摘要： The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).
摘要翻译： 本发明是一种用于在MOS晶体管结构中形成超陡掺杂分布的方法。 该方法包括在栅极电介质（50）下面形成含碳层（110），并在MOS晶体管的源极和漏极区域（80）形成。 含碳层（110）将防止掺杂剂扩散到栅极电介质层（50）正下方的区域（40）中。
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49.发明申请Control of dopant diffusion from buried layers in bipolar integrated circuits 审中-公开控制双极集成电路中埋层的掺杂剂扩散公开(公告)号：US20050250289A1
公开(公告)日：2005-11-10
申请号：US11180457
申请日：2005-07-13
申请人： Jeffrey Babcock , Angelo Pinto , Manfred Schiekofer , Scott Balster , Gregory Howard , Alfred Hausler
发明人： Jeffrey Babcock , Angelo Pinto , Manfred Schiekofer , Scott Balster , Gregory Howard , Alfred Hausler
IPC分类号： H01L21/331 , H01L21/8222 , H01L21/8228 , H01L29/73 , H01L29/737
CPC分类号： H01L29/66265 , H01L21/82285 , H01L29/66242 , H01L29/7317 , H01L29/7378
摘要： An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors (30, 50, 60), each having a buried collector region (26′). A carbon-bearing diffusion barrier (28c) is disposed over the buried collector region (26′), to inhibit the diffusion of dopant from the buried collector region (26′) into the overlying epitaxial layer (28). The diffusion barrier (28c) may be formed by incorporating a carbon source into the epitaxial formation of the overlying layer (28), or by ion implantation. In the case of ion implantation of carbon or SiGeC, masks (52, 62) may be used to define the locations of the buried collector regions (26′) that are to receive the carbon; for example, portions underlying eventual collector contacts (33, 44c) may be masked from the carbon implant so that dopant from the buried collector region (26′) can diffuse upward to meet the contact (33). MOS transistors (70, 80) including the diffusion barrier (28) are also disclosed.
摘要翻译： 公开了一种集成电路及其制造方法。 集成电路包括垂直双极晶体管（30,50,60），每个具有一个埋设集电极区域（26'）。 含碳扩散阻挡层（28c）设置在掩埋集电极区域（26'）之上，以阻止掺杂剂从掩埋的集电极区域（26'）扩散到上覆的外延层（28）中。 扩散阻挡层（28c）可以通过将碳源引入上覆层（28）的外延形成中，或通过离子注入来形成。 在碳或SiGeC的离子注入的情况下，可以使用掩模（52,62）来限定待接收碳的掩埋收集器区域（26'）的位置; 例如，最终的集电极触点（33,44c）下面的部分可以从碳注入掩模，使得来自掩埋的集电极区域（26'）的掺杂剂可向上扩散以满足触点（33）。 还公开了包括扩散阻挡层（28）的MOS晶体管（70,80）。
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50.发明授权On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits 有权片上加热用于多晶硅和多晶硅 - 锗 - 锗电阻器的电气修整和用于集成电路的电可编程保险丝公开(公告)号：US06958523B2
公开(公告)日：2005-10-25
申请号：US09949541
申请日：2001-09-07
CPC分类号： H01L27/0802 , H01C7/13 , H01C17/267 , H01L23/345 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit programmable structure (60) is formed for use a trim resistor and/or a programmable fuse. The programmable structure comprises placing heating elements (70) in close proximity to the programmable structure (60) to heat the programmable structure (60) during programming.
摘要翻译： 形成用于使用微调电阻器和/或可编程保险丝的集成电路可编程结构（60）。 可编程结构包括将加热元件（70）放置在可编程结构（60）附近以在编程期间加热可编程结构（60）。
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