-
1.发明申请Control of dopant diffusion from buried layers in bipolar integrated circuits 审中-公开控制双极集成电路中埋层的掺杂剂扩散公开(公告)号：US20050250289A1
公开(公告)日：2005-11-10
申请号：US11180457
申请日：2005-07-13
申请人： Jeffrey Babcock , Angelo Pinto , Manfred Schiekofer , Scott Balster , Gregory Howard , Alfred Hausler
发明人： Jeffrey Babcock , Angelo Pinto , Manfred Schiekofer , Scott Balster , Gregory Howard , Alfred Hausler
IPC分类号： H01L21/331 , H01L21/8222 , H01L21/8228 , H01L29/73 , H01L29/737
CPC分类号： H01L29/66265 , H01L21/82285 , H01L29/66242 , H01L29/7317 , H01L29/7378
摘要： An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors (30, 50, 60), each having a buried collector region (26′). A carbon-bearing diffusion barrier (28c) is disposed over the buried collector region (26′), to inhibit the diffusion of dopant from the buried collector region (26′) into the overlying epitaxial layer (28). The diffusion barrier (28c) may be formed by incorporating a carbon source into the epitaxial formation of the overlying layer (28), or by ion implantation. In the case of ion implantation of carbon or SiGeC, masks (52, 62) may be used to define the locations of the buried collector regions (26′) that are to receive the carbon; for example, portions underlying eventual collector contacts (33, 44c) may be masked from the carbon implant so that dopant from the buried collector region (26′) can diffuse upward to meet the contact (33). MOS transistors (70, 80) including the diffusion barrier (28) are also disclosed.
摘要翻译： 公开了一种集成电路及其制造方法。 集成电路包括垂直双极晶体管（30,50,60），每个具有一个埋设集电极区域（26'）。 含碳扩散阻挡层（28c）设置在掩埋集电极区域（26'）之上，以阻止掺杂剂从掩埋的集电极区域（26'）扩散到上覆的外延层（28）中。 扩散阻挡层（28c）可以通过将碳源引入上覆层（28）的外延形成中，或通过离子注入来形成。 在碳或SiGeC的离子注入的情况下，可以使用掩模（52,62）来限定待接收碳的掩埋收集器区域（26'）的位置; 例如，最终的集电极触点（33,44c）下面的部分可以从碳注入掩模，使得来自掩埋的集电极区域（26'）的掺杂剂可向上扩散以满足触点（33）。 还公开了包括扩散阻挡层（28）的MOS晶体管（70,80）。
-
2.发明申请公开(公告)号：US20050098093A1
公开(公告)日：2005-05-12
申请号：US10934188
申请日：2004-09-02
申请人： Jeffrey Babcock , Scott Balster , Alfred Haeusler , Angelo Pinto , Manfred Schiekofer , Philipp Steinmann , Badih El-Kareh
发明人： Jeffrey Babcock , Scott Balster , Alfred Haeusler , Angelo Pinto , Manfred Schiekofer , Philipp Steinmann , Badih El-Kareh
IPC分类号： C23C16/42 , C23C16/56 , C30B23/00 , C30B25/00 , C30B28/12 , C30B28/14 , H01L21/205 , H01L21/331 , H01L21/8222 , H01L29/737
CPC分类号： C23C16/42 , C23C16/56 , H01L21/02532 , H01L21/02576
摘要： A method of fabricating an epitaxial silicon-germanium layer for an integrated semiconductor device comprises the step of depositing an arsenic in-situ doped silicon-germanium layer, wherein arsenic and germanium are introduced subsequently into different regions of said silicon-germanium layer during deposition of said silicon-germanium layer. By separating arsenic from germanium any interaction between arsenic and germanium is avoided during deposition thereby allowing fabricating silicon-germanium layers with reproducible doping profiles.
摘要翻译： 制造用于集成半导体器件的外延硅 - 锗层的方法包括沉积砷原位掺杂硅 - 锗层的步骤，其中砷和锗随后在沉积期间被引入所述硅 - 锗层的不同区域 所述硅 - 锗层。 通过从锗中分离砷，可避免在沉积过程中砷和锗之间的相互作用，从而允许制造具有可重复掺杂分布的硅 - 锗层。
-
公开(公告)号：US20060197158A1
公开(公告)日：2006-09-07
申请号：US11380602
申请日：2006-04-27
IPC分类号： H01L27/12
CPC分类号： H01L29/66659 , H01L21/26506 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/823892 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/36 , H01L29/78612 , H01L29/78654
摘要： The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).
摘要翻译： 本发明是一种用于在MOS晶体管结构中形成超陡掺杂分布的方法。 该方法包括在栅极电介质（50）下面形成含碳层（110），并在MOS晶体管的源极和漏极区域（80）形成。 含碳层（110）将防止掺杂剂扩散到栅极电介质层（50）正下方的区域（40）中。
-
公开(公告)号：US20050258990A1
公开(公告)日：2005-11-24
申请号：US11182981
申请日：2005-07-15
IPC分类号： H01L21/02 , H01L21/768 , H01L23/34 , H01L23/525 , H03M1/10
CPC分类号： H01L21/76886 , H01L21/76888 , H01L23/345 , H01L23/5256 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit programmable structure (60) is formed for use a trim resistor and/or a programmable fuse. The programmable structure comprises placing heating elements (70) in close proximity to the programmable structure (60) to heat the programmable structure (60) during programming.
-
公开(公告)号：US20060175657A1
公开(公告)日：2006-08-10
申请号：US11362908
申请日：2006-02-28
IPC分类号： H01L29/76
CPC分类号： H01L29/66659 , H01L21/26506 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/823892 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/36 , H01L29/78612 , H01L29/78654
摘要： The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).
摘要翻译： 本发明是一种用于在MOS晶体管结构中形成超陡掺杂分布的方法。 该方法包括在栅极电介质（50）下面形成含碳层（110），并在MOS晶体管的源极和漏极区域（80）形成。 含碳层（110）将防止掺杂剂扩散到栅极电介质层（50）正下方的区域（40）中。
-
公开(公告)号：US06894366B2
公开(公告)日：2005-05-17
申请号：US09967187
申请日：2001-09-28
IPC分类号： H01L21/331 , H01L29/08 , H01L29/32 , H01L29/732 , H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/7322 , H01L29/0821 , H01L29/32
摘要： An improved BJT is described that maximizes both Bvceo and Ft/Fmax for optimum performance. Scattering centers are introduced in the collector region (80) of the BJT to improve Bvceo. The inclusion of the scattering centers allows the width of the collector region WCD (90) to be reduced leading to an improvement in Ft/Fmax.
摘要翻译： 描述了改进的BJT，使Bvceo和Ft / Fmax最大化以获得最佳性能。 散射中心引入BJT的收集器区域（80），以改善Bvceo。 包含散射中心允许减小集电极区域W（90）的宽度，从而改善Ft / Fmax。
-
7.发明申请Method for manufacturing and structure of semiconductor device with sinker contact region 有权具有沉降片接触区域的半导体器件的制造和结构的方法公开(公告)号：US20050037588A1
公开(公告)日：2005-02-17
申请号：US10939221
申请日：2004-09-10
IPC分类号： H01L21/331 , H01L29/417 , H01L27/082 , H01L21/8222
CPC分类号： H01L29/66272 , H01L29/41708
摘要： A method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer. A first isolation structure is formed adjacent at least a portion of the buried layer. A second isolation structure is formed adjacent at least a portion of the active region. A base layer is formed adjacent at least a portion of the active region. A dielectric layer is formed adjacent at least a portion of the base layer, and then at least part of the dielectric layer is removed at an emitter contact location and at a sinker contact location. An emitter structure is formed at the emitter contact location. Forming the emitter structure includes etching the semiconductor device at the sinker contact location to form a sinker contact region. The sinker contact region has a first depth. The method may also include forming a gate structure. Forming the gate structure includes etching the sinker contact region thereby increasing the first depth of the sinker contact region to a second depth.
摘要翻译： 半导体器件的制造方法包括形成半导体衬底的掩埋层。 在掩埋层的至少一部分附近形成有源区。 在掩埋层的至少一部分附近形成第一隔离结构。 在活性区域的至少一部分附近形成第二隔离结构。 在活性区域的至少一部分附近形成基底层。 在基底层的至少一部分附近形成电介质层，然后在发射极接触位置和沉降片接触位置移除介电层的至少一部分。 发射极结构形成在发射极接触位置。 形成发射极结构包括在沉降片接触位置蚀刻半导体器件以形成沉降片接触区域。 沉降片接触区域具有第一深度。 该方法还可以包括形成栅极结构。 形成栅极结构包括蚀刻沉降片接触区域，从而将沉降片接触区域的第一深度增加到第二深度。
-
公开(公告)号：US20070018225A1
公开(公告)日：2007-01-25
申请号：US11531840
申请日：2006-09-14
IPC分类号： H01L29/94
CPC分类号： H01L28/40 , H01L27/0805
摘要： An integrated stacked capacitor comprises a first capacitor film (46) of polycrystalline silicide (poly), a second capacitor film (48) and a first dielectric (26) sandwiched between the first capacitor film (46) and second capacitor film (48). A second dielectric (34) and a third capacitor film (50) are provided. The second dielectric (34) is sandwiched between the second capacitor film (48) and third capacitor film (50). A method for fabrication of an integrated stacked capacitor comprises the following sequence of steps: applying a polysilicide layer (20) to form the first capacitor film (46); applying a first dielectric (26); applying a first metallization layer (28) to form the second capacitor film (48); applying a second dielectric (34); and applying a second metallization layer (34) to form the third capacitor film (50).
摘要翻译： 集成堆叠电容器包括多晶硅化物（poly）的第一电容器膜（46），夹在第一电容器膜（46）和第二电容器膜（48）之间的第二电容器膜（48）和第一电介质（26）。 提供第二电介质（34）和第三电容膜（50）。 第二电介质（34）夹在第二电容器膜（48）和第三电容器膜（50）之间。 一种用于制造集成叠层电容器的方法包括以下步骤：施加多晶硅层（20）以形成第一电容器膜（46）; 施加第一电介质（26）; 施加第一金属化层（28）以形成第二电容器膜（48）; 施加第二电介质（34）; 以及施加第二金属化层（34）以形成所述第三电容器膜（50）。
-
公开(公告)号：US07736986B2
公开(公告)日：2010-06-15
申请号：US11740467
申请日：2007-04-26
IPC分类号： H01L21/20
CPC分类号： H01L28/40 , H01L27/0805
摘要： An integrated stacked capacitor comprises a first capacitor film (46) of polycrystalline silicide, a second capacitor film (48) and a first dielectric (26) sandwiched between the first capacitor film (46) and second capacitor film (48). A second dielectric (34) and a third capacitor film (50) are provided. The second dielectric (34) is sandwiched between the second capacitor film (48) and third capacitor film (50). A method for fabrication of an integrated stacked capacitor comprises the following sequence of steps: applying a polysilicide layer (20) to form the first capacitor film (46); applying a first dielectric (26); applying a first metallization layer (28) to form the second capacitor film (48); applying a second dielectric (34); and applying a second metallization layer (44) to form the third capacitor film (50).
摘要翻译： 集成堆叠电容器包括多晶硅化物的第一电容器膜（46），夹在第一电容器膜（46）和第二电容器膜（48）之间的第二电容器膜（48）和第一电介质（26）。 提供第二电介质（34）和第三电容膜（50）。 第二电介质（34）夹在第二电容器膜（48）和第三电容器膜（50）之间。 一种用于制造集成叠层电容器的方法包括以下步骤：施加多晶硅层（20）以形成第一电容器膜（46）; 施加第一电介质（26）; 施加第一金属化层（28）以形成第二电容器膜（48）; 施加第二电介质（34）; 以及施加第二金属化层（44）以形成所述第三电容器膜（50）。
-
公开(公告)号：US20080265368A1
公开(公告)日：2008-10-30
申请号：US11740467
申请日：2007-04-26
CPC分类号： H01L28/40 , H01L27/0805
摘要： An integrated stacked capacitor comprises a first capacitor film (46) of polycrystalline silicide (poly), a second capacitor film (48) and a first dielectric (26) sandwiched between the first capacitor film (46) and second capacitor film (48). A second dielectric (34) and a third capacitor film (50) are provided. The second dielectric (34) is sandwiched between the second capacitor film (48) and third capacitor film (50). A method for fabrication of an integrated stacked capacitor comprises the following sequence of steps: applying a polysilicide layer (20) to form the first capacitor film (46); applying a first dielectric (26); applying a first metallization layer (28) to form the second capacitor film (48); applying a second dielectric (34); and applying a second metallization layer (34) to form the third capacitor film (50).
摘要翻译： 集成堆叠电容器包括多晶硅化物（poly）的第一电容器膜（46），夹在第一电容器膜（46）和第二电容器膜（48）之间的第二电容器膜（48）和第一电介质（26）。 提供第二电介质（34）和第三电容膜（50）。 第二电介质（34）夹在第二电容器膜（48）和第三电容器膜（50）之间。 一种用于制造集成叠层电容器的方法包括以下步骤：施加多晶硅层（20）以形成第一电容器膜（46）; 施加第一电介质（26）; 施加第一金属化层（28）以形成第二电容器膜（48）; 施加第二电介质（34）; 以及施加第二金属化层（34）以形成所述第三电容器膜（50）。
-
-
-
-
-
-
-
-
-
搜索结果
15 条记录 (耗时 0.024 秒)
