公开(公告)号：US20210242170A1

公开(公告)日：2021-08-05

申请号：US16783132

申请日：2020-02-05

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Zhitao Cao ,  Kunzhong Hu ,  Jun Zhai

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H05K1/11 ,  H05K1/18

Abstract: Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (TO) density and routing quality for signals, while keeping power delivery feasible.

公开(公告)号：US20200176419A1

公开(公告)日：2020-06-04

申请号：US16503806

申请日：2019-07-05

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Kwan-Yu Lai ,  Kunzhong Hu ,  Vidhya Ramachandran

IPC: H01L25/065 ,  H01L21/66 ,  H01L23/48 ,  H01L23/60 ,  H01L21/768 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip including a reconstituted chip-level back endo of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

公开(公告)号：US20190189560A1

公开(公告)日：2019-06-20

申请号：US16250854

申请日：2019-01-17

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  David A. Secker ,  Huabo Chen ,  Zhenggang Cheng

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/14

Abstract: Routing structures including signal routing between die areas is described. In an embodiment, routing structures include signal lines with a characteristic thickness that is greater than a width. The signal lines may be twisted, and run directly underneath pads.

公开(公告)号：US10217708B1

公开(公告)日：2019-02-26

申请号：US15845978

申请日：2017-12-18

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  David A. Secker ,  Huabo Chen ,  Zhenggang Cheng

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/14 ,  H01L23/00 ,  H01L25/065

Abstract: Routing structures including signal routing between die areas is described. In an embodiment, routing structures include signal lines with a characteristic thickness that is greater than a width. The signal lines may be twisted, and run directly underneath pads.

公开(公告)号：US09607680B2

公开(公告)日：2017-03-28

申请号：US14196793

申请日：2014-03-04

Applicant: Apple Inc.

Inventor： Sanjay Dabral

IPC: G11C11/4074 ,  H01L25/065 ,  H01L23/64 ,  H01L23/522 ,  H01L27/108 ,  H01L49/02 ,  H01L23/498 ,  G11C7/02 ,  G11C5/14 ,  G11C29/02 ,  H01L23/00 ,  H01L25/18

CPC classification number: G11C11/4074 ,  G11C5/147 ,  G11C7/02 ,  G11C14/0018 ,  G11C29/021 ,  H01L23/49822 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/642 ,  H01L23/645 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1427 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: One or more integrated circuits including at least one integrated circuit that is fabricated in a DRAM fabrication process. Capacitors in the DRAM-fabricated integrated circuit can be used for decoupling for logic components of the integrated circuits, and may be used for fine-grain on-chip PMUs. The capacitors may be physically placed near the logic components for which the capacitors are providing decoupling capacitance, in an embodiment. The capacitors may be series connections of at least two capacitors, or at least one capacitor and a switch, to provide decoupling capacitance in the face of defects, in an embodiment. Embedded DRAM memories can be used instead of SRAM memories, with increased density and reduced leakage. More compact systems can be implemented using the integrated circuits.

公开(公告)号：US20250046715A1

公开(公告)日：2025-02-06

申请号：US18923503

申请日：2024-10-22

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Zhitao Cao ,  Kunzhong Hu ,  Jun Zhai

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H05K1/11 ,  H05K1/18

Abstract: Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (IO) density and routing quality for signals, while keeping power delivery feasible.

公开(公告)号：US12176803B2

公开(公告)日：2024-12-24

申请号：US18471868

申请日：2023-09-21

Applicant: Apple Inc.

Inventor： Chi Nung Ni ,  Sanjay Dabral

IPC: H02M1/15 ,  G06F1/3206 ,  H02M3/158

Abstract: Increases in current drawn from power supply nodes in a computer system can result in unwanted drops in the voltages of the power supply nodes until power supply circuits can compensate for the increased load. To lessen the effects of increases in load currents, a decoupling circuit that includes a diode may be coupled to the power supply node. During a charge mode, a control circuit applies a current to the diode to store charge in the diode. During a boost mode, the control circuit can couple the diode to the power supply node. When the voltage level of the power supply node begins to drop, the diode can source a current to the power supply node using the previously stored charge. The diode may be directly coupled to the power supply node or be part of a switch-based system that employs multiple diodes to increase the discharge voltage.

公开(公告)号：US20240103238A1

公开(公告)日：2024-03-28

申请号：US18458892

申请日：2023-08-30

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  SivaChandra Jangam

IPC: G02B6/42

CPC classification number: G02B6/428 ,  G02B6/4279 ,  G02B6/4283 ,  G02B6/4293

Abstract: A system in package structure and method of fabrication using wafer reconstitution are described. In an embodiment a 3D system includes a mid-layer interposer a first package level underneath the mid-layer interposer and a second package level over the mid-layer interposer. Second package level components can be bonded to the mid-layer interposer with metal-metal bonds and optionally dielectric-dielectric bonds, while the first package level components can be bonded to the mid-layer interposer with dielectric-dielectric and optionally metal-metal bonds. Dies within the first and/or second package levels may optionally be connected with one or more optical interconnect paths.

公开(公告)号：US20240047353A1

公开(公告)日：2024-02-08

申请号：US18488561

申请日：2023-10-17

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Jung-Cheng Yeh ,  Kunzhong Hu ,  Raymundo Camenforte ,  Thomas Hoffmann

IPC: H01L23/528 ,  H01L23/538 ,  H01L23/48 ,  H01L25/065 ,  H01L23/58

CPC classification number: H01L23/528 ,  H01L23/5386 ,  H01L23/481 ,  H01L25/0655 ,  H01L25/0652 ,  H01L23/585 ,  H01L22/20

Abstract: Multi-die structures and methods of fabrication are described. In an embodiment, a multi-die structure includes a first die, a second die, and die-to-die routing connecting the first die to the second die. The die-to-die interconnection may be monolithically integrated as a chip-level die-to-die routing, or external package-level die-to-die routing.

公开(公告)号：US11735526B2

公开(公告)日：2023-08-22

申请号：US17699563

申请日：2022-03-21

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Zhitao Cao ,  Kunzhong Hu ,  Jun Zhai

IPC: H01L23/528 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H05K1/11 ,  H05K1/18 ,  H01L23/00

CPC classification number: H01L23/5286 ,  H01L23/49816 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0652 ,  H05K1/111 ,  H05K1/181 ,  H01L24/16 ,  H01L2224/16225 ,  H05K2201/10378 ,  H05K2201/10734

Abstract: Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (IO) density and routing quality for signals, while keeping power delivery feasible.