公开(公告)号：US20250006552A1

公开(公告)日：2025-01-02

申请号：US18753144

申请日：2024-06-25

Applicant: Applied Materials Inc.

Inventor： Liqi Wu ,  Rongjun Wang ,  Feng Q. Liu ,  Qihao Zhu ,  Jiang Lu ,  David Thompson ,  Xianmin Tang

IPC: H01L21/768 ,  H01L21/3213

Abstract: Embodiments of the disclosure relate to methods of selectively depositing a metallic material after forming a flowable polymer film to protect a substrate surface within a feature. A first metal liner is deposited by physical vapor deposition (PVD). The flowable polymer film is formed on the first metal liner on the bottom. A portion of the first metal liner is selectively removed from the top surface and the at least one sidewall. The flowable polymer film is removed. In some embodiments, the cycle of depositing a metal liner, forming a flowable polymer film, removing a portion of the metal liner, and removing the flowable polymer film is repeated at least once. A metal layer is deposited on the plurality of metal liners (e.g., first metal liner and the second metal liner) and the metal layer is free of seams or voids.

公开(公告)号：US20240191353A1

公开(公告)日：2024-06-13

申请号：US18077225

申请日：2022-12-07

Applicant: Applied Materials, Inc.

Inventor： Yoon Ah Shin ,  Bencherki Mebarki ,  Joung Joo Lee ,  Xianmin Tang ,  Thai Cheng Chua ,  Christian W. Valencia

IPC: C23C16/455 ,  H01J37/32 ,  H01L21/02

CPC classification number: C23C16/45536 ,  H01J37/32192 ,  H01L21/02057

Abstract: Embodiments of the disclosure relate to methods for reducing metal oxide layers to pure metal using microwave radiation. Specific embodiments provide methods of reducing a native metal oxide on a metal interconnect within a substrate feature comprising dielectric sidewalls. In some embodiments, surrounding dielectric materials are undamaged by the disclosed processes.

公开(公告)号：US20230113961A1

公开(公告)日：2023-04-13

申请号：US18081276

申请日：2022-12-14

Applicant: Applied Materials, Inc.

Inventor： Bencherki Mebarki ,  Komal S. Garde ,  Kishor Kalathiparambil ,  Joung Joo Lee ,  Xianmin Tang

IPC: C23C14/34 ,  H01J37/34 ,  H01J37/32 ,  C23C14/14 ,  C23F4/00 ,  C23C14/54

Abstract: Embodiments of the disclosure relate to methods for enlarging the opening width of substrate features by reducing the overhang of deposited films. Some embodiments of the disclosure utilize a high power bias pulse to etch the deposited film near the opening of the substrate feature. Some embodiments of the disclosure etch the deposited film without damaging the underlying substrate.

公开(公告)号：US11562909B2

公开(公告)日：2023-01-24

申请号：US16881145

申请日：2020-05-22

Applicant: Applied Materials, Inc.

Inventor： Yu Lei ,  Xuesong Lu ,  Tae Hong Ha ,  Xianmin Tang ,  Andrew Nguyen ,  Tza-Jing Gung ,  Philip A. Kraus ,  Chung Nang Liu ,  Hui Sun ,  Yufei Hu

IPC: H01L21/67 ,  H01L21/311 ,  H01L21/02 ,  H01J37/32 ,  H01L21/683 ,  H01L21/3105 ,  H01L21/8234

Abstract: Described is a process to clean up junction interfaces for fabricating semiconductor devices involving forming low-resistance electrical connections between vertically separated regions. An etch can be performed to remove silicon oxide on silicon surface at the bottom of a recessed feature. Described are methods and apparatus for etching up the bottom oxide of a hole or trench while minimizing the effects to the underlying epitaxial layer and to the dielectric layers on the field and the corners of metal gate structures. The method for etching features involves a reaction chamber equipped with a combination of capacitively coupled plasma and inductive coupled plasma. CHxFy gases and plasma are used to form protection layer, which enables the selectively etching of bottom silicon dioxide by NH3—NF3 plasma. Ideally, silicon oxide on EPI is removed to ensure low-resistance electric contact while the epitaxial layer and field/corner dielectric layers are—etched only minimally or not at all.

公开(公告)号：US11527437B2

公开(公告)日：2022-12-13

申请号：US17022058

申请日：2020-09-15

Applicant: APPLIED MATERIALS, INC.

Inventor： Lanlan Zhong ,  Fuhong Zhang ,  Gang Shen ,  Feng Chen ,  Rui Li ,  Xiangjin Xie ,  Tae Hong Ha ,  Xianmin Tang

IPC: H01L21/768 ,  G11B5/31 ,  C23C16/455

Abstract: Methods and apparatus for filling features on a substrate are provided herein. In some embodiments, a method of filling features on a substrate includes: depositing a first metallic material on the substrate and within a feature disposed in the substrate in a first process chamber via a chemical vapor deposition (CVD) process at a first temperature; depositing a second metallic material on the first metallic material in a second process chamber at a second temperature and at a first bias power to form a seed layer of the second metallic material; etching the seed layer in the second process chamber at a second bias power greater than the first bias power to form an intermix layer within the feature comprising the first metallic material and the second metallic material; and heating the substrate to a third temperature greater than the second temperature, causing a reflow of the second metallic material.

公开(公告)号：US20220328348A1

公开(公告)日：2022-10-13

申请号：US17853150

申请日：2022-06-29

Applicant: Applied Materials, Inc.

Inventor： Rui Li ,  Xiangjin Xie ,  Tae Hong Ha ,  Xianmin Tang ,  Lu Chen

IPC: H01L21/768 ,  C23C16/455 ,  C23C16/34

Abstract: Methods of forming copper interconnects are described. A doped tantalum nitride layer formed on a copper layer on a substrate has a first amount of dopant. The doped tantalum nitride layer is exposed to a plasma comprising one or more of helium or neon to form a treated doped tantalum nitride layer with a decreased amount of dopant. Apparatus for performing the methods are also described.

公开(公告)号：US11424132B2

公开(公告)日：2022-08-23

申请号：US16590755

申请日：2019-10-02

Applicant: APPLIED MATERIALS, INC.

Inventor： Takashi Kuratomi ,  Avgerinos Gelatos ,  Tae Hong Ha ,  Xuesong Lu ,  Szuheng Ho ,  Wei Lei ,  Mark Lee ,  Raymond Hung ,  Xianmin Tang

IPC: H01L21/3205 ,  H01L21/285 ,  H01L21/02 ,  H01L21/321 ,  C23C16/02 ,  H01L21/768 ,  C23C16/455 ,  C23C16/06 ,  C23C16/34 ,  C23C14/06 ,  C23C16/56

Abstract: Methods and apparatus for producing a reduced contact resistance for cobalt-titanium structures. In some embodiments, a method comprises depositing a titanium layer using a chemical vapor deposition (CVD) process, depositing a titanium nitride layer on the titanium layer using an atomic layer deposition (ALD) process, depositing a first cobalt layer on the titanium nitride layer using a physical vapor deposition (PVD) process, and depositing a second cobalt layer on the first cobalt layer using a CVD process.

公开(公告)号：US20210351136A1

公开(公告)日：2021-11-11

申请号：US16909148

申请日：2020-06-23

Applicant: Applied Materials, Inc.

Inventor： Gang Shen ,  Feng Chen ,  Yizhak Sabba ,  Tae Hong Ha ,  Xianmin Tang ,  Zhiyuan Wu ,  Wenjing Xu

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

Abstract: Described are microelectronic device comprising a dielectric layer formed on a substrate, a feature 206 comprising a gap defined in the dielectric layer, a barrier layer on the dielectric layer, a two metal liner film on the barrier layer and a gap fill metal on the two metal liner. Embodiments provide a method of forming an microelectronic device comprising the two metal liner film on the barrier layer.

公开(公告)号：US11037768B2

公开(公告)日：2021-06-15

申请号：US15448996

申请日：2017-03-03

Applicant: APPLIED MATERIALS, INC.

Inventor： Xiaodong Wang ,  Joung Joo Lee ,  Fuhong Zhang ,  Martin Lee Riker ,  Keith A. Miller ,  William Fruchterman ,  Rongjun Wang ,  Adolph Miller Allen ,  Shouyin Zhang ,  Xianmin Tang

IPC: H01J37/34 ,  C23C14/35 ,  C23C14/54 ,  H01L21/768 ,  H01L21/285

Abstract: Methods and apparatus for controlling the ion fraction in physical vapor deposition processes are disclosed. In some embodiments, a process chamber for processing a substrate having a given diameter includes: an interior volume and a target to be sputtered, the interior volume including a central portion and a peripheral portion; a rotatable magnetron above the target to form an annular plasma in the peripheral portion; a substrate support disposed in the interior volume to support a substrate having the given diameter; a first set of magnets disposed about the body to form substantially vertical magnetic field lines in the peripheral portion; a second set of magnets disposed about the body and above the substrate support to form magnetic field lines directed toward a center of the support surface; a first power source to electrically bias the target; and a second power source to electrically bias the substrate support.

公开(公告)号：US10815561B2

公开(公告)日：2020-10-27

申请号：US16295328

申请日：2019-03-07

Applicant: APPLIED MATERIALS, INC.

Inventor： Joung Joo Lee ,  Bencherki Mebarki ,  Xianmin Tang ,  Keith Miller ,  Sree Rangasai Kesapragada ,  Sudarsan Srinivasan

IPC: C23C14/04 ,  C23C14/34 ,  H01L21/285 ,  H01L21/02

Abstract: Methods and apparatus for asymmetric selective physical vapor deposition (PVD) are provided herein. In some embodiments, a method for physical vapor deposition (PVD) includes providing a stream of a first material from a first PVD source towards a surface of a substrate at a first non-perpendicular angle to the plane of the substrate surface, directing the stream of the first material through a first collimator having at least one opening to limit an angular range of first material passing through the at least one opening; depositing the first material only on a top portion and a first sidewall of at least one feature formed on the substrate surface, and linearly scan the substrate through the stream of first material via the substrate support to deposit the first material only on a top portion and a first sidewall of all features formed on the substrate.