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    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    41.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
    半导体器件及其制造方法

    公开(公告)号：US20070111424A1

    公开(公告)日：2007-05-17

    申请号：US11620576

    申请日：2007-01-05

    申请人： Hideomi Suzawa ,  Koji Ono ,  Toru Takayama ,  Tatsuya Arao ,  Shunpei Yamazaki

    发明人： Hideomi Suzawa ,  Koji Ono ,  Toru Takayama ,  Tatsuya Arao ,  Shunpei Yamazaki

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/124 ,  H01L21/32136 ,  H01L27/1214 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78684 ,  H01L2029/7863

    摘要： There has been a problem that the manufacturing process is complicated and the number of processes is increased when a TFT with an LDD structure or a TFT with a GOLD structure is formed. In a method of manufacturing a semiconductor device, after low concentration impurity regions (24, 25) are formed in a second doping process, a width of the low concentration impurity region which is overlapped with the third electrode (18c) and a width of the low concentration impurity region which is not overlapped with the third electrode can be freely controlled by a fourth etching process. Thus, in a region overlapped with the third electrode, a relaxation of electric field concentration is achieved and then a hot carrier injection can be prevented. And, in the region which is not overlapped with the third electrode, the off-current value can be suppressed.

    摘要翻译： 当形成具有LDD结构的TFT或具有GOLD结构的TFT时，存在制造过程复杂并且处理次数增加的问题。 在制造半导体器件的方法中，在第二掺杂工艺中形成低浓度杂质区（24,25）之后，与第三电极（18c）重叠的低浓度杂质区的宽度和 可以通过第四蚀刻工艺来自由地控制不与第三电极重叠的低浓度杂质区域。 因此，在与第三电极重叠的区域中，实现电场浓度的松弛，然后可以防止热载流子注入。 并且，在不与第三电极重叠的区域中，可以抑制截止电流值。

    Semiconductor device and manufacturing method thereof
    42.
    发明授权
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号：US07161177B2

    公开(公告)日：2007-01-09

    申请号：US10833080

    申请日：2004-04-28

    申请人： Hideomi Suzawa ,  Koji Ono ,  Toru Takayama ,  Tatsuya Arao ,  Shunpei Yamazaki

    发明人： Hideomi Suzawa ,  Koji Ono ,  Toru Takayama ,  Tatsuya Arao ,  Shunpei Yamazaki

    IPC分类号： H01L29/04 ,  H01L31/0376

    CPC分类号： H01L27/124 ,  H01L21/32136 ,  H01L27/1214 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78684 ,  H01L2029/7863

    摘要： There has been a problem that the manufacturing process is complicated and the number of processes is increased when a TFT with an LDD structure or a TFT with a GOLD structure is formed. In a method of manufacturing a semiconductor device, after low concentration impurity regions (24, 25) are formed in a second doping process, a width of the low concentration impurity region which is overlapped with the third electrode (18c) and a width of the low concentration impurity region which is not overlapped with the third electrode can be freely controlled by a fourth etching process. Thus, in a region overlapped with the third electrode, a relaxation of electric field concentration is achieved and then a hot carrier injection can be prevented. And, in the region which is not overlapped with the third electrode, the off-current value can be suppressed.

    摘要翻译： 当形成具有LDD结构的TFT或具有GOLD结构的TFT时，存在制造过程复杂并且处理次数增加的问题。 在制造半导体器件的方法中，在第二掺杂工艺中形成低浓度杂质区（24,25）之后，与第三电极（18c）重叠的低浓度杂质区的宽度和 可以通过第四蚀刻工艺来自由地控制不与第三电极重叠的低浓度杂质区域。 因此，在与第三电极重叠的区域中，实现电场浓度的松弛，然后可以防止热载流子注入。 并且，在不与第三电极重叠的区域中，可以抑制截止电流值。

    Semiconductor device
    44.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08546912B2

    公开(公告)日：2013-10-01

    申请号：US13440157

    申请日：2012-04-05

    申请人： Shunpei Yamazaki ,  Tatsuya Arao

    发明人： Shunpei Yamazaki ,  Tatsuya Arao

    IPC分类号： H01L21/08

    CPC分类号： H01L27/1266 ,  G06K19/07749 ,  G06K19/07775 ,  G06K19/07779 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/13 ,  H01Q1/2208 ,  H01Q1/2283 ,  H01Q1/38 ,  H01Q23/00

    摘要： A semiconductor device such as an ID chip of the present invention includes an integrated circuit using a semiconductor element formed by using a thin semiconductor film, and an antenna connected to the integrated circuit. It is preferable that the antenna is formed integrally with the integrated circuit, since the mechanical strength of an ID chip can be enhanced. Note that the antenna used in the present invention also includes a conducting wire that is wound round circularly or spirally and fine particles of a soft magnetic material are arranged between the conducting wires. Specifically, an insulating layer in which fine particles of a soft magnetic material are arranged between the conducting wires. Specifically, an insulating layer in which fine particles of a soft magnetic material are included is arranged between the conducting wires.

    摘要翻译： 本发明的ID芯片等半导体装置包括使用由半导体薄膜形成的半导体元件的集成电路和与集成电路连接的天线。 优选地，天线与集成电路一体形成，因为可以提高ID芯片的机械强度。 注意，本发明中使用的天线还包括绕圆形或螺旋状地缠绕的导线，并且在导线之间布置有软磁性材料的细小颗粒。 具体而言，在导线之间配置有软磁性材料的细微粒子的绝缘层。 具体而言，在导线之间配置有包含软磁性材料的微粒的绝缘层。

    Semiconductor device and manufacturing method thereof
    45.
    发明授权
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号：US08470647B2

    公开(公告)日：2013-06-25

    申请号：US11620576

    申请日：2007-01-05

    申请人： Hideomi Suzawa ,  Koji Ono ,  Toru Takayama ,  Tatsuya Arao ,  Shunpei Yamazaki

    发明人： Hideomi Suzawa ,  Koji Ono ,  Toru Takayama ,  Tatsuya Arao ,  Shunpei Yamazaki

    IPC分类号： H01L21/84

    CPC分类号： H01L27/124 ,  H01L21/32136 ,  H01L27/1214 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78684 ,  H01L2029/7863

    摘要： There has been a problem that the manufacturing process is complicated and the number of processes is increased when a TFT with an LDD structure or a TFT with a GOLD structure is formed. In a method of manufacturing a semiconductor device, after low concentration impurity regions (24, 25) are formed in a second doping process, a width of the low concentration impurity region which is overlapped with the third electrode (18c) and a width of the low concentration impurity region which is not overlapped with the third electrode can be freely controlled by a fourth etching process. Thus, in a region overlapped with the third electrode, a relaxation of electric field concentration is achieved and then a hot carrier injection can be prevented. And, in the region which is not overlapped with the third electrode, the off-current value can be suppressed.

    摘要翻译： 当形成具有LDD结构的TFT或具有GOLD结构的TFT时，存在制造过程复杂并且处理次数增加的问题。 在制造半导体器件的方法中，在第二掺杂工艺中形成低浓度杂质区（24,25）之后，与第三电极（18c）重叠的低浓度杂质区的宽度和 不与第三电极重叠的低浓度杂质区域可以通过第四蚀刻工艺自由地控制。 因此，在与第三电极重叠的区域中，实现电场浓度的松弛，然后可以防止热载流子注入。 并且，在不与第三电极重叠的区域中，可以抑制截止电流值。

    Semiconductor device
    47.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08159043B2

    公开(公告)日：2012-04-17

    申请号：US10583365

    申请日：2005-03-09

    申请人： Shunpei Yamazaki ,  Tatsuya Arao

    发明人： Shunpei Yamazaki ,  Tatsuya Arao

    IPC分类号： H01L21/08

    CPC分类号： H01L27/1266 ,  G06K19/07749 ,  G06K19/07775 ,  G06K19/07779 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/13 ,  H01Q1/2208 ,  H01Q1/2283 ,  H01Q1/38 ,  H01Q23/00

    摘要： A semiconductor device such as an ID chip of the present invention includes an integrated circuit using a semiconductor element formed by using a thin semiconductor film, and an antenna connected to the integrated circuit. It is preferable that the antenna is formed integrally with the integrated circuit, since the mechanical strength of an ID chip can be enhanced. Note that the antenna used in the present invention also includes a conducting wire that is wound round circularly or spirally and fine particles of a soft magnetic material are arranged between the conducting wires. Specifically, an insulating layer in which fine particles of a soft magnetic material are arranged between the conducting wires. Specifically, an insulating layer in which fine particles of a soft magnetic material are included is arranged between the conducting wires.

    摘要翻译： 本发明的ID芯片等半导体装置包括使用由半导体薄膜形成的半导体元件的集成电路和与集成电路连接的天线。 优选地，天线与集成电路一体形成，因为可以提高ID芯片的机械强度。 注意，本发明中使用的天线还包括绕圆形或螺旋状地缠绕的导线，并且在导线之间布置有软磁性材料的细小颗粒。 具体而言，在导线之间配置有软磁性材料的细微粒子的绝缘层。 具体而言，在导线之间配置有包含软磁性材料的微粒的绝缘层。

    LIGHT EMITTING DEVICE
    49.
    发明申请
    LIGHT EMITTING DEVICE 有权

    公开(公告)号：US20120012888A1

    公开(公告)日：2012-01-19

    申请号：US13241351

    申请日：2011-09-23

    申请人： Shunpei Yamazaki ,  Jun Koyama ,  Tatsuya Arao ,  Munehiro Azami

    发明人： Shunpei Yamazaki ,  Jun Koyama ,  Tatsuya Arao ,  Munehiro Azami

    IPC分类号： H01L27/15

    CPC分类号： H01L27/3265 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/3246 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/78633

    摘要： A light emitting device is provided which can prevent a change in gate voltage due to leakage or other causes and at the same time can prevent the aperture ratio from lowering. A capacitor storage is formed from a connection wiring line, an insulating film, and a capacitance wiring line. The connection wiring line is formed over a gate electrode and an active layer of a TFT of a pixel, and is connected to the active layer. The insulating film is formed on the connection wiring line. The capacitance wiring line is formed on the insulating film. This structure enables the capacitor storage to overlap the TFT, thereby increasing the capacity of the capacitor storage while keeping the aperture ratio from lowering. Accordingly, a change in gate voltage due to leakage or other causes can be avoided to prevent a change in luminance of an OLED and flickering of screen in analog driving.

    Light emitting device
    50.
    发明授权
    Light emitting device 有权
    发光装置

    公开(公告)号：US07808002B2

    公开(公告)日：2010-10-05

    申请号：US11773172

    申请日：2007-07-03

    申请人： Shunpei Yamazaki ,  Jun Koyama ,  Tatsuya Arao ,  Munehiro Azami

    发明人： Shunpei Yamazaki ,  Jun Koyama ,  Tatsuya Arao ,  Munehiro Azami

    IPC分类号： H01L29/04

    CPC分类号： H01L27/3265 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/3246 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/78633

    摘要： A light emitting device is provided which can prevent a change in gate voltage due to leakage or other causes and at the same time can prevent the aperture ratio from lowering. A capacitor storage is formed from a connection wiring line, an insulating film, and a capacitance wiring line. The connection wiring line is formed over a gate electrode and an active layer of a TFT of a pixel, and is connected to the active layer. The insulating film is formed on the connection wiring line. The capacitance wiring line is formed on the insulating film. This structure enables the capacitor storage to overlap the TFT, thereby increasing the capacity of the capacitor storage while keeping the aperture ratio from lowering. Accordingly, a change in gate voltage due to leakage or other causes can be avoided to prevent a change in luminance of an OLED and flickering of screen in analog driving.

    摘要翻译： 提供一种可以防止由于泄漏或其它原因引起的栅极电压变化并且同时可以防止开口率降低的发光器件。 电容器存储器由连接布线，绝缘膜和电容布线形成。 连接布线形成在栅电极和像素的TFT的有源层上，并与有源层连接。 绝缘膜形成在连接布线上。 电容布线形成在绝缘膜上。 这种结构使得电容器存储与TFT重叠，从而在保持开口率降低的同时增加电容器存储的容量。 因此，可以避免由于泄漏或其他原因导致的栅极电压的变化，以防止OLED的亮度变化和模拟驱动中屏幕的闪烁。