公开(公告)号：US07741177B2

公开(公告)日：2010-06-22

申请号：US11879179

申请日：2007-07-16

Applicant: Chih-Hsin Wang

Inventor： Chih-Hsin Wang

IPC: H01L21/336 ,  H01L21/331 ,  H01L21/8238

CPC classification number: H01L27/115 ,  G11C16/0416 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/7885 ,  H01L29/792

Abstract: A method of providing a memory cell comprises providing a semiconductor substrate including a body of a first conductivity type, first and second regions of a second conductivity type and a channel between the first and second regions; arranging a first insulator layer adjacent to the substrate; arranging a charge storage region adjacent to the first insulator layer; arranging a second insulator layer adjacent to the charge storage region; arranging a first conductive region adjacent to the second insulator layer; arranging a layer adjacent to the first conductive region; arranging a second conductive region adjacent to the layer; and increasing mechanical stress of at least one of the first and second conductive regions. The second conductive region overlaps the first conductive region at an overlap surface, and wherein a line perpendicular to the overlap surface intersects at least a portion of the charge storage region.

Abstract translation: 提供存储单元的方法包括：提供包括第一导电类型的主体，第二导​​电类型的第一和第二区域以及第一和第二区域之间的通道的半导体衬底; 布置与所述基板相邻的第一绝缘体层; 配置与所述第一绝缘体层相邻的电荷存储区域; 布置与电荷存储区域相邻的第二绝缘体层; 布置与所述第二绝缘体层相邻的第一导电区域; 布置与所述第一导电区域相邻的层; 布置与所述层相邻的第二导电区域; 以及增加所述第一和第二导电区域中的至少一个的机械应力。 第二导电区域在重叠表面处与第一导电区域重叠，并且其中垂直于重叠表面的线与电荷存储区域的至少一部分相交。

公开(公告)号：US07613041B2

公开(公告)日：2009-11-03

申请号：US11464404

申请日：2006-09-25

Applicant: Chih-Hsin Wang

Inventor： Chih-Hsin Wang

IPC: G11C11/34

CPC classification number: G11C16/3418 ,  G11C16/3427

Abstract: Methods and apparatus on charges injection using piezo-ballistic-charges injection mechanism are provided for semiconductor device and nonvolatile memory device. The device comprises a strain source, an injection filter, a first conductive region, a second conductive region, and a third conductive region. The strain source permits piezo-effect in ballistic charges transport to enable the piezo-ballistic-charges injection mechanism in device operations. The injection filter permits transporting of charge carriers of one polarity type from the first conductive region, through the filter, and through the second conductive region to the third conductive region while blocking the transport of charge carriers of an opposite polarity from the second conductive region to the first conductive region. The present invention further provides an energy band engineering method permitting the devices be operated without suffering from disturbs, from dielectric breakdown, from impact ionization, and from undesirable RC effects.

Abstract translation: 为半导体器件和非易失性存储器件提供使用压电弹药注入机构的电荷注入的方法和装置。 该装置包括应变源，注射过滤器，第一导电区域，第二导电区域和第三导电区域。 应变源允许在弹道电荷输送中的压电效应，使得能够在器件操作中实现压电弹药注入机制。 注入过滤器允许将一种极性类型的电荷载体从第一导电区域通过滤波器传输，并且通过第二导电区域传输到第三导电区域，同时阻止相反极性的电荷载体从第二导电区域传输到 第一导电区域。 本发明进一步提供一种能量带工程方法，其允许在不受到电介质击穿，不受冲击电离和不期望的RC影响的干扰的情况下操作装置。

公开(公告)号：US07547601B2

公开(公告)日：2009-06-16

申请号：US11978875

申请日：2007-10-30

Applicant: Chih-Hsin Wang

Inventor： Chih-Hsin Wang

IPC: H01L21/331 ,  H01L21/336

CPC classification number: H01L27/11568 ,  G11C16/0416 ,  G11C16/0466 ,  H01L21/26586 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42336 ,  H01L29/47 ,  H01L29/66636 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/792

Abstract: A method of providing a memory cell includes providing a body of a semiconductor material having a first conductivity type, arranging a filter of a conductor-filter system in contact with a first conductor of the conductor-filter system, arranging at least portion of a second conductor of a conductor-insulator system in contact with the filter, arranging a first insulator of the conductor-insulator system in contact with the second conductor at an interface, arranging a first region spaced from the second conductor, arranging a channel of the body between the first region and the second conductor, arranging a second insulator adjacent to the first region, arranging a charge storage region between the first and the second insulators, arranging a first portion of a word-line adjacent to and insulated from the charge storage region, and arranging a second portion of the word-line adjacent to and insulated from the body.

Abstract translation: 提供存储单元的方法包括提供具有第一导电类型的半导体材料的主体，布置与导体过滤器系统的第一导体接触的导体过滤系统的滤波器，将至少部分第二导体 与过滤器接触的导体 - 绝缘体系统的导体，在接口处布置导体 - 绝缘体系统的第一绝缘体与第二导体接触，布置与第二导体间隔开的第一区域，将主体的沟道布置在 所述第一区域和所述第二导体布置与所述第一区域相邻的第二绝缘体，在所述第一绝缘体和所述第二绝缘体之间布置电荷存储区域，布置与所述电荷存储区域相邻并与所述电荷存储区域绝缘的字线的第一部分， 并且将所述字线的第二部分布置成与所述主体相邻并且与所述主体绝缘。

公开(公告)号：US20080203464A1

公开(公告)日：2008-08-28

申请号：US11932481

申请日：2007-10-31

Applicant: Chih-Hsin Wang

Inventor： Chih-Hsin Wang

IPC: H01L29/76 ,  H01L21/336

CPC classification number: H01L27/11568 ,  B82Y10/00 ,  G11C16/0416 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/792

Abstract: A memory device, array and method of arranging where the memory device includes a memory cell region including a plurality of memory cells. Each memory cell includes a source, a drain and a channel between the source and the drain, a channel dielectric, a charge storage region and an electrically alterable conductor-material system in proximity to the charge storage region. Cell lines extend among the memory cells. A connection region is provided for electrically coupling contacts and one or more of the cell lines. A non-memory region has embedded logic. Memory cells are arrayed at a cell pitch, with cell lines extending from cell to cell and arrayed substantially at the cell pitch, and with contacts arrayed substantially at the cell pitch forming a high density memory device.

Abstract translation: 一种存储器件，阵列和方法，其布置存储器件包括包括多个存储器单元的存储单元区域的位置。 每个存储单元包括源极，漏极和源极和漏极之间的沟道，沟道电介质，电荷存储区域和靠近电荷存储区域的电可改变的导体材料系统。 单元线在存储单元之间延伸。 提供连接区域用于电耦合触点和一个或多个细胞系。 非内存区域具有嵌入式逻辑。 存储器单元以单元间距排列，细胞系从单元延伸到单元并基本上以单元间距排列，并且基本上以单元间距排列的接触形成高密度存储器件。

公开(公告)号：US07411244B2

公开(公告)日：2008-08-12

申请号：US11234646

申请日：2005-09-23

Applicant: Chih-Hsin Wang

Inventor： Chih-Hsin Wang

IPC: H01L29/06 ,  H01L21/336

CPC classification number: H01L27/11568 ,  G11C16/0416 ,  G11C16/0466 ,  H01L21/26586 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42336 ,  H01L29/47 ,  H01L29/66636 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/792

Abstract: Nonvolatile memory cells having a conductor-filter system, a conductor-insulator system, and a charge-injection system are provided. The conductor-filter system provides band-pass filtering function, charge-filtering function, and mass-filtering function to charge-carriers flows. The conductor-insulator system provides Image-Force barrier lowering effect to collect charge-carriers. The charge-injection system includes the conductor-filter system and the conductor-insulator system, wherein the filter of the conductor-filter system contacts the conductor of the conductor-insulator system. Apparatus on cell architecture are provided for the nonvolatile memory cells. Additionally, apparatus on array architectures are provided for constructing the nonvolatile memory cells in memory array. Method on manufacturing such memory cells and array architectures are provided.

Abstract translation: 提供具有导体滤波器系统，导体 - 绝缘体系统和电荷注入系统的非易失性存储单元。 导体滤波器系统为电荷载流子提供带通滤波功能，电荷滤波功能和质量滤波功能。 导体 - 绝缘体系统提供图像强制屏障降低效应以收集电荷载体。 电荷注入系统包括导体 - 滤波器系统和导体 - 绝缘体系统，其中导体 - 滤波器系统的滤波器接触导体 - 绝缘体系统的导体。 为非易失性存储单元提供了单元结构的装置。 此外，提供了阵列架构上的装置用于构建存储器阵列中的非易失性存储单元。 提供了制造这种存储单元和阵列架构的方法。

公开(公告)号：US20080070390A1

公开(公告)日：2008-03-20

申请号：US11980154

申请日：2007-10-30

Applicant: Chih-Hsin Wang

Inventor： Chih-Hsin Wang

IPC: H01L21/425

CPC classification number: H01L27/115 ,  G11C16/0416 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/42336 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/7885 ,  H01L29/792

Abstract: A method comprises providing a first conductive region, arranging a second conductive region adjacent to and insulated from the first conductive region by a dielectric region, arranging a third region adjacent to and insulated from the second conductive region, and adjusting mechanical stress to at least one of the first conductive region and the second conductive region.

Abstract translation: 一种方法包括提供第一导电区域，通过电介质区域布置邻近第一导电区域并与第一导电区域绝缘的第二导电区域，布置邻近第二导电区域并与第二导电区域绝缘的第三区域，以及将机械应力调整至至少一个 的第一导电区域和第二导电区域。

公开(公告)号：US20060290504A1

公开(公告)日：2006-12-28

申请号：US11356584

申请日：2006-02-17

Applicant: Chih-Hsin Wang

Inventor： Chih-Hsin Wang

IPC: G08B13/14

CPC classification number: G08B13/2445

Abstract: A system for tracking elements employing fixed tags that are permanently attached to elements. The tags include radio-frequency (RF) communication units that are adapted for wireless communication with RF communicators. The RF tags are permanently affixed to elements as part of the manufacturing of products such as cell phones, PDA's, computers, routers and other electronic equipment. The RF tags are installed during manufacturing in a manner that resists tampering and interference. The RF tags are installed with mechanical barriers to access and are hidden from view in non-user accessible locations.

公开(公告)号：US20060213988A1

公开(公告)日：2006-09-28

申请号：US11091647

申请日：2005-03-28

Applicant: Chih-Hsin Wang

Inventor： Chih-Hsin Wang

IPC: G06Q30/00 ,  G06F7/00

CPC classification number: H01L23/544 ,  G06Q10/00 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2223/54433 ,  H01L2223/54446 ,  H01L2223/54486 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/0106 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: A management system for tracking elements through steps and stages of a chain employing fixed tags permanently attached to elements that progress through the steps and stages. The elements are tracked by the fixed tags from an initial stage, through multiple work-in-process stages to a final stage of the chain. The fixed tags include radio-frequency (RF) communication units that have wireless communication with RF communicators in one or more of the stages of the supply chain. The wireless communications between the RF tags and the RF communicators operate with a tag communication protocol that defines the operations and sequences for storing information into and retrieval of information from tags. The hierarchy of data storage in RF tags, in RF communicators and otherwise in storage locations in the system is controlled to operate within the memory hierarchy.

Abstract translation: 用于通过链条的步骤和阶段跟踪元件的管理系统，其使用永久附着到通过步骤和阶段进行的元素的固定标签。 这些元素由固定的标签从初始阶段跟踪，通过多个在制品阶段到链的最后阶段。 固定标签包括与供应链的一个或多个阶段中的RF通信器进行无线通信的射频（RF）通信单元。 RF标签和RF通信器之间的无线通信使用标签通信协议进行操作，标签通信协议定义用于将信息存储到标签中并从其检索信息的操作和序列。 在RF标签，RF通信器中以及在系统中的存储位置中的数据存储层级被控制以在存储器层次结构内操作。

公开(公告)号：US07015102B2

公开(公告)日：2006-03-21

申请号：US11006237

申请日：2005-04-13

Applicant: Chih-Hsin Wang

Inventor： Chih-Hsin Wang

IPC: H10L21/336

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7885

Abstract: A method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes an electrical conductive floating gate formed in a trench in a semiconductor substrate, and an electrical conductive control gate having a portion disposed over and insulated from the floating gate. An electrical conductive tunneling gate is disposed over and insulated from the control gate by an insulating layer to form a tri-layer structure permitting both electron and hole charges tunneling through at similar tunneling rate. Spaced apart source and drain regions are formed with the source region disposed adjacent to and insulated from a lower portion of the floating gate, and with the drain region disposed adjacent to and insulated from an upper portion of the floating gate with a channel region formed therebetween and along a sidewall of the trench.

Abstract translation: 一种形成浮栅存储器单元阵列的方法，以及由此形成的阵列，其中每个存储单元包括形成在半导体衬底中的沟槽中的导电浮动栅极，以及导电控制栅极，其具有设置在绝缘上的部分 从浮动门。 导电隧道栅极通过绝缘层设置在控制栅极之上并与控制栅极绝缘，以形成三层结构，允许电子和空穴电荷以类似的隧穿速率隧穿。 间隔开的源极和漏极区域形成有源极区域，其设置为与浮置栅极的下部相邻并与其绝缘，并且漏极区域设置成与浮置栅极的上部相邻并与之隔绝，其中沟道区域形成在其间 并且沿着沟槽的侧壁。

公开(公告)号：US20060035424A1

公开(公告)日：2006-02-16

申请号：US10919555

申请日：2004-08-16

Applicant: Chih-Hsin Wang

Inventor： Chih-Hsin Wang

IPC: H01L21/8234

CPC classification number: G11C16/14 ,  G11C16/0416 ,  H01L29/42332 ,  H01L29/7885 ,  H01L29/792

Abstract: A nonvolatile memory cell is provided. The memory cell includes a storage transistor and an injector in a well of an n-type conductivity. The well is formed in a semiconductor substrate of a p-type conductivity. The storage transistor comprises a source, a drain, a channel, and a charge storage region. The source and the drain are formed in the well and having the p-type conductivity with the channel of the well defined therebetween. The charge storage region is disposed over and insulated from the channel region by an insulator. Further provided are methods operating the memory cell, including means for injecting electrons from the channel through the insulator onto the charge storage region and means for injecting holes from the injector through the well through the channel through the insulator onto the charge storage region. The memory cell can be implemented in a conventional logic CMOS process.