公开(公告)号：US20050275015A1

公开(公告)日：2005-12-15

申请号：US10710006

申请日：2004-06-11

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/49 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/785 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/66553 ,  H01L29/66795

摘要： A method and structure for tuning a threshold voltage of nFET and pFET devices in a double-gate CMOS integrated circuit structure, wherein the method comprises performing a PSP (post silicide processing) electrical test on the double-gate CMOS integrated circuit structure, determining nFET and pFET threshold voltages during the PSP test, and implanting the double-gate CMOS integrated circuit structure with an alkali metal ion, wherein the step of implanting adjusts the nFET and pFET threshold voltages by an amount required to match desired off-currents for the nFET and pFET devices. According to the method, prior to the step of performing, the method comprises forming a fin structure over an isolation layer, forming source/drain regions over the fin structure, depositing a gate oxide layer adjacent to the source/drain regions, and forming a gate region over the gate oxide layer and the fin structure. The metal ion comprises any of cesium and rubidium.

摘要翻译： 一种用于在双栅极CMOS集成电路结构中调谐nFET和pFET器件的阈值电压的方法和结构，其中该方法包括在双栅极CMOS集成电路结构上执行PSP（后硅化物处理）电测试，确定nFET 和PSFET测试期间的pFET阈值电压，以及用碱金属离子注入双栅极CMOS集成电路结构，其中注入步骤将nFET和pFET阈值电压调整为与nFET匹配期望的截止电流所需的量 和pFET器件。 根据该方法，在执行步骤之前，该方法包括在隔离层上形成翅片结构，在翅片结构上形成源极/漏极区域，在栅极/漏极区域附近沉积栅极氧化物层，并形成 栅极区域在栅极氧化物层和鳍结构上。 金属离子包括任何铯和铷。

公开(公告)号：US20070212834A1

公开(公告)日：2007-09-13

申请号：US11748576

申请日：2007-05-15

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L21/336

CPC分类号： H01L29/42328 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7881

摘要： Disclosed is a multiple-gate transistor that includes a channel region and source and drain regions at ends of the channel region. A gate oxide is positioned between a logic gate and the channel region and a first insulator is formed between a floating gate and the channel region. The first insulator is thicker than the gate oxide. The floating gate is electrically insulated from other structures. Also, a second insulator is positioned between a programming gate and the floating gate. Voltage in the logic gate causes the transistor to switch on and off, while stored charge in the floating gate adjusts the threshold voltage of the transistor. The transistor can comprise a fin-type field effect transistor (FinFET), where the channel region comprises the middle portion of a fin structure and the source and drain regions comprise end portions of the fin structure.

摘要翻译： 公开了一种多栅极晶体管，其在沟道区的端部包括沟道区和源极和漏极区。 栅极氧化物位于逻辑栅极和沟道区之间，并且在浮置栅极和沟道区域之间形成第一绝缘体。 第一绝缘体比栅极氧化物厚。 浮动栅极与其他结构电绝缘。 此外，第二绝缘体位于编程门和浮动栅极之间。 逻辑门中的电压导致晶体管导通和截止，而浮置栅极中的存储电荷调节晶体管的阈值电压。 晶体管可以包括鳍式场效应晶体管（FinFET），其中沟道区域包括鳍结构的中间部分，并且源区和漏区包括鳍结构的端部。

公开(公告)号：US20070158763A1

公开(公告)日：2007-07-12

申请号：US11275514

申请日：2006-01-11

申请人： Brent Anderson ,  Victor Chan ,  Edward Nowak

发明人： Brent Anderson ,  Victor Chan ,  Edward Nowak

IPC分类号： H01L29/76 ,  H01L21/3205

CPC分类号： H01L29/66477 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/28518 ,  H01L29/1083 ,  H01L29/42376 ,  H01L29/66507 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78654

摘要： A semiconductor transistor with an expanded top portion of a gate and a method for forming the same. The semiconductor transistor with an expanded top portion of a gate includes (a) a semiconductor region which includes a channel region and first and second source/drain regions; the channel region is disposed between the first and second source/drain regions, (b) a gate dielectric region in direct physical contact with the channel region, and (c) a gate electrode region which includes a top portion and a bottom portion. The bottom portion is in direct physical contact with the gate dielectric region. A first width of the top portion is greater than a second width of the bottom portion. The gate electrode region is electrically insulated from the channel region by the gate dielectric region.

摘要翻译： 具有扩大的栅极顶部的半导体晶体管及其形成方法。 具有扩大的栅极顶部的半导体晶体管包括：（a）包括沟道区和第一和第二源极/漏极区的半导体区; 沟道区域设置在第一和第二源极/漏极区域之间，（b）与沟道区域直接物理接触的栅极电介质区域，以及（c）包括顶部和底部的栅电极区域。 底部部分与栅介质区域直接物理接触。 顶部的第一宽度大于底部的第二宽度。 栅电极区域通过栅极电介质区域与沟道区域电绝缘。

公开(公告)号：US20070111410A1

公开(公告)日：2007-05-17

申请号：US11622169

申请日：2007-01-11

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/78603

摘要： An integrated circuit structure has a buried oxide (BOX) layer above a substrate, and a first-type fin-type field effect transistor (FinFET) and a second-type FinFET above the BOX layer. The second region of the BOX layer includes a seed opening to the substrate. The top of the first-type FinFET and the second-type FinFET are planar with each other. A first region of the BOX layer below the first FinFET fin is thicker above the substrate when compared to a second region of the BOX layer below the second FinFET fin. Also, the second FinFET fin is taller than the first FinFET fin. The height difference between the first fin and the second fin permits the first-type FinFET to have the same drive strength as the second-type FinFET.

摘要翻译： 集成电路结构在衬底上方具有掩埋氧化物（BOX）层，以及在BOX层上方的第一型鳍型场效应晶体管（FinFET）和第二类型FinFET。 BOX层的第二区域包括到基板的种子开口。 第一型FinFET和第二型FinFET的顶部彼此平坦。 当与第二FinFET鳍片下面的BOX层的第二区域相比时，第一FinFET鳍片下面的BOX层的第一区域比衬底上方更厚。 此外，第二个FinFET鳍片比第一个FinFET鳍片高。 第一鳍片和第二鳍片之间的高度差允许第一类型的FinFET具有与第二类型FinFET相同的驱动强度。

公开(公告)号：US20060292772A1

公开(公告)日：2006-12-28

申请号：US11160457

申请日：2005-06-24

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L21/8234 ,  H01L21/336 ,  H01L21/84

CPC分类号： H01L21/823437 ,  H01L21/823412 ,  H01L21/84 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/78609 ,  Y10S257/903

摘要： Disclosed is a method of forming a pair of transistors by epitaxially growing a pair of silicon fins on a silicon germanium fin on a bulk wafer. In one embodiment a gate conductor between the fins is isolated from a conductor layer on the bulk wafer so a front gate may be formed. In another embodiment a gate conductor between the fins contacts a conductor layer on the bulk wafer so a back gate may be formed. In yet another embodiment both of the previous structures are simultaneously formed on the same bulk wafer. The method allow the pairs of transistors to be formed with a variety of features (e.g., strained fins, a space between two fins that is approximately 0.5 to 3 times greater than a width of a single fin, a first dielectric layer on the inner sidewalls of each pair of fins with a different thickness and/or a different dielectric material than a second dielectric layer on the outer sidewalls of each pair of fins, etc.).

摘要翻译： 公开了通过在体晶片上的硅锗翅片上外延生长一对硅散热片来形成一对晶体管的方法。 在一个实施例中，翅片之间的栅极导体与体晶片上的导体层隔离，因此可以形成前栅极。 在另一个实施例中，翅片之间的栅极导体接触体晶片上的导体层，因此可形成背栅。 在另一个实施例中，两个先前的结构同时形成在相同的体晶片上。 该方法允许成对的晶体管形成有各种特征（例如，应变翅片，两个翅片之间的空间，比单个鳍片的宽度大约0.5至3倍，内侧壁上的第一介电层 每个翅片具有与每对翅片的外侧壁上的第二介电层不同的厚度和/或不同的电介质材料等）。

公开(公告)号：US20060286724A1

公开(公告)日：2006-12-21

申请号：US11160361

申请日：2005-06-21

申请人： Brent Anderson ,  Matthew Breitwisch ,  Edward Nowak

发明人： Brent Anderson ,  Matthew Breitwisch ,  Edward Nowak

IPC分类号： H01L21/84 ,  H01L29/76

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

摘要： Disclosed is a tri-gate field effect transistor with a back gate and the associated methods of forming the transistor. Specifically, a back gate is incorporated into a lower portion of a fin. A tri-gate structure is formed on the fin and is electrically isolated from the back gate. The back gate can be used to control the threshold voltage of the FET. In one embodiment the back gate extends to an n-well in a p-type silicon substrate. A contact to the n-well allows electrical voltage to be applied to the back gate. A diode created between the n-well and p-substrate isolates the current flowing through the n-well from other devices on the substrate so that the back gate can be independently biased. In another embodiment the back gate extends to n-type polysilicon layer on an insulator layer on a p-type silicon substrate. A contact to the n-type polysilicon layer allows electrical voltage to be applied to the back gate. A trench isolation structure extending through the polysilicon layer to the insulator layer isolates current flowing through the polysilicon layer from other devices on the silicon substrate.

摘要翻译： 公开了具有背栅的三栅场效应晶体管和形成晶体管的相关方法。 具体地说，后门结合在翅片的下部。 三栅结构形成在翅片上并与后门电隔离。 背栅可用于控制FET的阈值电压。 在一个实施例中，背栅极延伸到p型硅衬底中的n阱。 与n阱的接触允许将电压施加到后门。 在n阱和p衬底之间产生的二极管将流过n阱的电流与衬底上的其他器件隔离，使得后栅极可以被独立地偏置。 在另一个实施例中，背栅极延伸到p型硅衬底上的绝缘体层上的n型多晶硅层。 与n型多晶硅层的接触允许电压施加到后门。 通过多晶硅层延伸到绝缘体层的沟槽隔离结构将流过多晶硅层的电流与硅衬底上的其它器件隔离。

公开(公告)号：US20060228862A1

公开(公告)日：2006-10-12

申请号：US10907568

申请日：2005-04-06

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L21/00

CPC分类号： H01L21/823425 ,  H01L21/823475 ,  H01L27/0207 ,  H01L29/78 ,  H01L29/7851 ,  H01L2029/7858

摘要： A complementary metal oxide semiconductor field effect transistor (CMOS FET) design layout and method of fabrication are disclosed that provide a long gate and dense pitch in which gate contacts are positioned directly on top of the gates, and source and drain contacts are made into contact CA bars with contact pads outside the RX (active silicon conductor) region of the FET.

摘要翻译： 公开了互补金属氧化物半导体场效应晶体管（CMOS FET）的制造布局和制造方法，其提供了长栅极和密集间距，其中栅极触点直接位于栅极的顶部，并且源极和漏极触点被形成接触 CA焊条在FET的RX（有源硅导体）区域外部具有接触焊盘。

公开(公告)号：US20060183289A1

公开(公告)日：2006-08-17

申请号：US11401786

申请日：2006-04-11

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L21/336

CPC分类号： H01L27/1211 ,  H01L21/845 ,  H01L27/11 ,  H01L29/66795 ,  H01L29/785 ,  Y10S257/903

摘要： A compact semiconductor structure having back gate(s) for controlling threshold voltages and associated method of formation is disclosed. Fabrication of the semiconductor structure starts with a semiconductor region formed directly on an underlying electrically isolating layer. Then, a mandrel and a spacer are formed on the semiconductor region. Next, a back gate region is formed separated from the semiconductor region by a back gate isolating layer and covered by an inter-gate isolating layer. Next, a portion of the semiconductor region beneath the mandrel is removed so as to form an active region adjacent to the removed portion of the semiconductor region. Finally, a main gate region is formed in place of the removed portion of the semiconductor region and on the inter-gate isolating layer. The main gate region is separated from the active region by a main gate isolating layer and separated from the back gate region by the inter-gate isolating layer.

公开(公告)号：US20060163673A1

公开(公告)日：2006-07-27

申请号：US11340354

申请日：2006-01-26

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/66553 ,  H01L29/66795

摘要： A field effect transistor (FET) comprising an isolation layer, a source region positioned over the isolation layer, a drain region positioned over the isolation layer, a bifurcated silicide gate region positioned over the channel region, and a gate oxide layer adjacent to the gate region, wherein the gate oxide layer comprises an alkali metal ion implanted at a dosage calculated based on threshold voltage test data provided by a post silicide electrical test conducted on said FET, wherein the alkali metal ion comprises any of cesium and rubidium.

摘要翻译： 包括隔离层的场效应晶体管（FET），位于隔离层上方的源极区域，位于隔离层上方的漏极区域，位于沟道区域上方的分叉硅化物栅极区域以及邻近栅极的栅氧化层 区，其中所述栅极氧化物层包含以基于通过在所述FET上进行的后硅化物电测试提供的阈值电压测试数据计算的剂量注入的碱金属离子，其中所述碱金属离子包含任何铯和铷。

公开(公告)号：US20050275922A1

公开(公告)日：2005-12-15

申请号：US10710050

申请日：2004-06-15

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： G02F1/03 ,  G02F1/07 ,  G02F1/19

CPC分类号： G02F1/19 ,  G02F2201/16 ,  G02F2202/34 ,  H01L29/785

摘要： The invention relates to optical switching. Rapid, low-power optical switching is achieved by selectively substantially depleting majority carriers in a plurality of planes of semiconducting material to alter their transmissive response to incoming radiation.

摘要翻译： 本发明涉及光切换。 通过选择性地基本消耗半导体材料的多个平面中的多数载流子来改变其对入射辐射的透射响应来实现快速的低功率光开关。