公开(公告)号：US20080185652A1

公开(公告)日：2008-08-07

申请号：US12060922

申请日：2008-04-02

申请人： Toshijaru Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger ,  Chung H. Lam ,  Gerhard I. Meijer

发明人： Toshijaru Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger ,  Chung H. Lam ,  Gerhard I. Meijer

IPC分类号： H01L23/62 ,  H01L21/8234

CPC分类号： H01L27/0629 ,  H01L27/101 ,  H01L27/24

摘要： Disclosed are a semiconductor structure and a method that allow for simultaneous voltage/current conditioning of multiple memory elements in a nonvolatile memory device with multiple memory cells. The structure and method incorporate the use of a resistor connected in series with the memory elements to limit current passing through the memory elements. Specifically, the method and structure incorporate a blanket temporary series resistor on the wafer surface above the memory cells and/or permanent series resistors within the memory cells. During the conditioning process, these resistors protect the transition metal oxide in the individual memory elements from damage (i.e., burn-out), once it has been conditioned.

摘要翻译： 公开了一种半导体结构和方法，其允许在具有多个存储器单元的非易失性存储器件中同时对多个存储器元件进行电压/电流调节。 该结构和方法结合使用与存储器元件串联连接的电阻器来限制电流通过存储器元件。 具体地，该方法和结构在存储器单元上方的晶片表面上和/或存储器单元内的永久串联电阻器上并入一个橡皮布暂时串联电阻器。 在调节过程中，一旦调节了这些电阻，这些电阻就可以保护各个存储元件中的过渡金属氧化物免受损坏（即烧坏）。

公开(公告)号：US07393779B2

公开(公告)日：2008-07-01

申请号：US11163786

申请日：2005-10-31

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Larry A. Nesbit

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Larry A. Nesbit

IPC分类号： H01L21/4763

CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144

摘要： Sublithographic contact apertures through a dielectric are formed in a stack of dielectric, hardmask and oxide-containing seed layer. An initial aperture through the seed layer receives a deposition of oxide by liquid phase deposition, which adheres selectively to the exposed vertical walls of the aperture in the seed layer. The sublithographic aperture, reduced in size by the thickness of the added material, defines a reduced aperture in the hardmask. The reduced hardmask then defines the sublithographic aperture through the dielectric.

摘要翻译： 通过电介质的亚光刻接触孔形成在电介质，硬掩模和含氧化物种子层的堆叠中。 通过种子层的初始孔径通过液相沉积接收氧化物沉积，该相沉积选择性地粘附到种子层中的孔的暴露的垂直壁。 通过所添加的材料的厚度减小尺寸的亚光刻孔径在硬掩模中限定了减小的孔径。 缩小的硬掩模然后限定通过电介质的亚光刻孔。

公开(公告)号：US07368712B2

公开(公告)日：2008-05-06

申请号：US11164792

申请日：2005-12-06

申请人： Carol A. Boye ,  Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Carol A. Boye ,  Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： G01N23/00 ,  G21K7/00

CPC分类号： G01Q60/42 ,  G01Q70/12

摘要： A Y-shaped carbon nanotube atomic force microscope probe tip and methods comprise a shaft portion; a pair of angled arms extending from a same end of the shaft portion, wherein the shaft portion and the pair of angled arms comprise a chemically modified carbon nanotube, and wherein the chemically modified carbon nanotube is modified with any of an amine, carboxyl, fluorine, and metallic component. Preferably, each of the pair of angled arms comprises a length of at least 200 nm and a diameter between 10 and 200 nm. Moreover, the chemically modified carbon nanotube is preferably adapted to allow differentiation between substrate materials to be probed. Additionally, the chemically modified carbon nanotube is preferably adapted to allow fluorine gas to flow through the chemically modified carbon nanotube onto a substrate to be characterized. Furthermore, the chemically modified carbon nanotube is preferably adapted to chemically react with a substrate surface to be characterized.

摘要翻译： Y型碳纳米管原子力显微镜探针头和方法包括轴部分; 一对成角度的臂，其从所述轴部的同一端延伸，其中所述轴部和所述一对成角度的臂包括化学改性的碳纳米管，并且其中所述化学改性的碳纳米管用胺，羧基，氟 ，和金属成分。 优选地，一对成角度的臂中的每一个包括至少200nm的长度和10和200nm之间的直径。 此外，化学改性的碳纳米管优选适于允许待探测的基底材料之间的分化。 此外，化学改性的碳纳米管优选适于使氟气通过化学改性的碳纳米管流动到待表征的基底上。 此外，化学改性的碳纳米管优选适于与要表征的基材表面发生化学反应。

公开(公告)号：US07362412B2

公开(公告)日：2008-04-22

申请号：US10904601

申请日：2004-11-18

申请人： Steven J. Holmes ,  Mark C. Hakey ,  Toshiharu Furukawa ,  David V. Horak

发明人： Steven J. Holmes ,  Mark C. Hakey ,  Toshiharu Furukawa ,  David V. Horak

IPC分类号： G03B27/52 ,  G03B27/42 ,  G03B27/58

CPC分类号： G03F7/70341 ,  G03F7/70925

摘要： A method and apparatus for reduction and prevention of residue formation and removal of residues formed in an immersion lithography tool. The apparatus including incorporation of a cleaning mechanism within the immersion head of an immersion lithographic system or including a cleaning mechanism in a cleaning station of an immersion lithographic system.

摘要翻译： 一种用于减少和防止残留物形成和去除在浸没式光刻工具中形成的残留物的方法和装置。 该设备包括在浸没式光刻系统的浸没头部内并入清洁机构，或者在浸没式光刻系统的清洁站中包括清洁机构。

公开(公告)号：US07358140B2

公开(公告)日：2008-04-15

申请号：US11163968

申请日：2005-11-04

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L27/1052 ,  Y10S438/95

摘要： A structure fabrication method. The method comprises providing a design structure that includes (i) a design substrate and (ii) M design normal regions on the design substrate, wherein M is a positive integer greater than 1. Next, N design sacrificial regions are added between two adjacent design normal regions of the M design normal regions, wherein N is a positive integer. Next, an actual structure is provided that includes (i) an actual substrate corresponding to the design substrate, (ii) a to-be-etched layer on the actual substrate, and (iii) a memory layer on the to-be-etched layer. Next, an edge printing process is performed on the memory layer so as to form (a) M normal memory portions aligned with the M design normal regions and (b) N sacrificial memory portions aligned with the N design sacrificial regions.

摘要翻译： 一种结构制造方法。 该方法包括提供一种设计结构，其包括（i）设计基板和（ii）设计基板上的M设计法线区域，其中M是大于1的正整数。接下来，在两个相邻设计之间添加N个设计牺牲区域 M正常区域的正常区域，其中N是正整数。 接下来，提供实际结构，其包括（i）与设计基板对应的实际基板，（ii）实际基板上的待蚀刻层，以及（iii）待蚀刻的存储层 层。 接下来，对存储层执行边缘打印处理，以便形成（a）与M设计法线区域对准的M个正常存储器部分和（b）与N个设计牺牲区域对准的N个牺牲存储器部分。

公开(公告)号：US07351648B2

公开(公告)日：2008-04-01

申请号：US11335372

申请日：2006-01-19

申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Chung Hon Lam

发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Chung Hon Lam

IPC分类号： H01L21/44 ,  H01L21/76

CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76885

摘要： Methods for fabricating a semiconductor device include forming a first layer on an underlying layer, forming a hardmask on the first layer, and patterning holes through the hardmask and first layer. An overhang is formed extending over sides of the holes. A conformal layer is deposited over the overhang and in the holes until the conformal layer closes off the holes to form a void/seam in each hole. The void/seam in each hole is exposed by etching back a top surface. The void/seam in each hole is extended to the underlying layer.

摘要翻译： 制造半导体器件的方法包括在下层上形成第一层，在第一层上形成硬掩模，以及通过硬掩模和第一层图形化孔。 形成在孔的侧面上延伸的突出端。 保形层沉积在悬垂孔和孔中，直到共形层封闭孔，以在每个孔中形成空隙/接缝。 每个孔中的空隙/接缝通过蚀刻顶部表面而暴露出来。 每个孔中的空隙/接缝延伸到下层。

公开(公告)号：US07348610B2

公开(公告)日：2008-03-25

申请号：US10906557

申请日：2005-02-24

申请人： Toshiharu Furukawa ,  David V. Horak ,  Charles W. Koburger, III ,  Leathen Shi, III

发明人： Toshiharu Furukawa ,  David V. Horak ,  Charles W. Koburger, III ,  Leathen Shi, III

IPC分类号： H01L27/10

CPC分类号： H01L29/045 ,  H01L21/76254 ,  H01L21/823807 ,  H01L27/1203

摘要： A semiconductor on insulator substrate and a method of fabricating the substrate. The substrate including: a first crystalline semiconductor layer and a second crystalline semiconductor layer; and an insulating layer bonding a bottom surface of the first crystalline semiconductor layer to a top surface of the second crystalline semiconductor layer, a first crystal direction of the first crystalline semiconductor layer aligned relative to a second crystal direction of the second crystalline semiconductor layer, the first crystal direction different from the second crystal direction.

摘要翻译： 绝缘体上半导体衬底及其制造方法。 所述基板包括：第一晶体半导体层和第二晶体半导体层; 以及将所述第一晶体半导体层的底面与所述第二结晶半导体层的顶面接合的绝缘层，所述第一结晶半导体层相对于所述第二结晶半导体层的第二晶体方向排列的第一晶体方向， 第一晶体方向与第二晶体方向不同。

公开(公告)号：US07345370B2

公开(公告)日：2008-03-18

申请号：US10905590

申请日：2005-01-12

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L23/48

CPC分类号： H01L21/76885 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/76852 ,  H01L21/76862 ,  H01L21/76871 ,  H01L21/76874 ,  H01L23/5283 ,  H01L23/53209 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Conductive sidewall spacer structures are formed using a method that patterns structures (mandrels) and activates the sidewalls of the structures. Metal ions are attached to the sidewalls of the structures and these metal ions are reduced to form seed material. The structures are then trimmed and the seed material is plated to form wiring on the sidewalls of the structures.

摘要翻译： 使用图案结构（心轴）并激活结构的侧壁的方法形成导电侧壁间隔结构。 金属离子附着在结构的侧壁上，这些金属离子被还原成晶种。 然后对结构进行修整，并且种子材料被电镀以在结构的侧壁上形成布线。

公开(公告)号：US07329613B2

公开(公告)日：2008-02-12

申请号：US10906899

申请日：2005-03-11

申请人： Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/76885 ,  C23C16/045 ,  H01L21/28562 ,  H01L21/76852 ,  H01L23/53209 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a conductive wire structure for a semiconductor device includes defining a mandrel on a substrate, forming a conductive wire material on the mandrel by atomic layer deposition, and forming a liner material around the conductive wire material by atomic layer deposition.

摘要翻译： 一种用于形成半导体器件的导线结构的方法包括在基片上限定心轴，通过原子层沉积在心轴上形成导线材料，并通过原子层沉积在导线材料周围形成衬垫材料。

公开(公告)号：US07265013B2

公开(公告)日：2007-09-04

申请号：US11162662

申请日：2005-09-19

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Kirk D. Peterson

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Kirk D. Peterson

IPC分类号： H01L21/8242 ,  H01L21/336

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/28132

摘要： A structure fabrication method. The method comprises providing a structure which comprises (a) a to-be-etched layer, (b) a memory region, (c) a positioning region, (d) and a capping region on top of one another. Then, the positioning region is indented. Then, a conformal protective layer is formed on exposed-to-ambient surfaces of the structure. Then, portions of the conformal protective layer are removed so as to expose the capping region to the surrounding ambient without exposing the memory region to the surrounding ambient. Then, the capping region is removed so as to expose the positioning region to the surrounding ambient. Then, the positioning region is removed so as to expose the memory region to the surrounding ambient. Then, the memory region is directionally etched with remaining portions of the conformal protection layer serving as a blocking mask.

摘要翻译： 一种结构制造方法。 该方法包括提供一种结构，该结构包括：（a）待蚀刻层，（b）存储区域，（c）位于彼此顶部的定位区域（d）和封盖区域。 然后，定位区域缩进。 然后，在结构的暴露于环境的表面上形成保形层。 然后，去除保形层的一部分，以将覆盖区域暴露于周围环境，而不会使存储区域暴露于周围环境。 然后，去除封盖区域，以将定位区域暴露于周围环境。 然后，移除定位区域，以将存储区域暴露于周围环境。 然后，存储区域被定向蚀刻，保形层的剩余部分用作阻挡掩模。