公开(公告)号：US08259510B2

公开(公告)日：2012-09-04

申请号：US12772238

申请日：2010-05-03

Applicant: Ching-Te Chuang ,  Hao-I Yang ,  Jihi-Yu Lin ,  Shyh-Chyi Yang ,  Ming-Hsien Tu ,  Wei Hwang ,  Shyh-Jye Jou ,  Kun-Ti Lee ,  Hung-Yu Li

Inventor： Ching-Te Chuang ,  Hao-I Yang ,  Jihi-Yu Lin ,  Shyh-Chyi Yang ,  Ming-Hsien Tu ,  Wei Hwang ,  Shyh-Jye Jou ,  Kun-Ti Lee ,  Hung-Yu Li

IPC: G11C7/00

CPC classification number: G11C11/412

Abstract: A disturb-free static random access memory cell includes: a latch circuit having a first access terminal and a second access terminal; a first switching circuit having a first bit transferring terminal coupled to the first access terminal, a first control terminal coupled to a first write word line, and a second bit transferring terminal; a second switching circuit having a third bit transferring terminal coupled to the second access terminal, a second control terminal coupled to a second write word line, and a fourth bit transferring terminal coupled to the second bit transferring terminal; a third switching circuit having a fifth bit transferring terminal coupled to the fourth bit transferring terminal, a third control terminal coupled to a word line, and a sixth bit transferring terminal coupled to a bit line; and a sensing amplifier coupled to the bit line, for determining a bit value appearing at the bit line.

Abstract translation: 无干扰的静态随机存取存储单元包括：具有第一接入终端和第二接入终端的锁存电路; 第一切换电路，具有耦合到第一接入终端的第一比特传送终端，耦合到第一写字线的第一控制终端和第二比特传送终端; 第二切换电路，具有耦合到第二接入终端的第三比特传送终端，耦合到第二写字线的第二控制终端，以及耦合到第二比特传送终端的第四比特传送终端。 第三开关电路，具有耦合到第四位转移终端的第五位转移终端，耦合到字线的第三控制端和耦合到位线的第六位转移端; 以及耦合到位线的感测放大器，用于确定出现在位线处的位值。

公开(公告)号：US20120057399A1

公开(公告)日：2012-03-08

申请号：US12876682

申请日：2010-09-07

Applicant: Shyh-Jye JOU ,  Jhih-Yu Lin ,  Ching-Te Chuang ,  Ming-Hsien Tu ,  Ming-Chien Tsai

Inventor： Shyh-Jye JOU ,  Jhih-Yu Lin ,  Ching-Te Chuang ,  Ming-Hsien Tu ,  Ming-Chien Tsai

IPC: G11C11/00

CPC classification number: G11C11/413

Abstract: The present invention discloses an asymmetric virtual-ground single-ended SRAM and a system thereof, wherein a first inverter is coupled to a high potential and a virtual ground, and wherein the first inverter and a second inverter form a latch loop, and wherein a third inverter is electrically connected with the second inverter, and wherein the third inverter and the second inverter are jointly coupled to the high potential and a ground. A write word line and a read word line control an access transistor and a pass transistor to undertake writing and reading of signals. A plurality of asymmetric virtual-ground single-ended SRAMs forms a memory system.

Abstract translation: 本发明公开了一种非对称虚拟地单端SRAM及其系统，其中第一反相器耦合到高电位和虚拟地，并且其中第一反相器和第二反相器形成锁存环，并且其中 第三反相器与第二反相器电连接，并且其中第三反相器和第二反相器共同耦合到高电位和接地。 写字线和读字线控制存取晶体管和传输晶体管以进行信号的写入和读取。 多个非对称虚拟地单端SRAM形成存储器系统。

公开(公告)号：US20120033522A1

公开(公告)日：2012-02-09

申请号：US12852759

申请日：2010-08-09

Applicant: Ching-Te Chuang ,  Yi-Wei Lin ,  Chia-Cheng Chen ,  Wei-Chiang Shih

Inventor： Ching-Te Chuang ,  Yi-Wei Lin ,  Chia-Cheng Chen ,  Wei-Chiang Shih

IPC: G11C8/08

CPC classification number: G11C8/08 ,  G11C11/413

Abstract: A Random Access Memory (RAM) is provided. The RAM includes a plurality of word-line drivers, at least a first tracking transistor and a second tracking transistor. Each word-line driver has an input node receiving a decoding signal, a power node receiving an operation voltage and a driving node driving a word-line. In an embodiment, the first tracking transistor has two channel terminal nodes respectively coupled to the driving node of one of the word-line driver and a channel terminal node of the second tracking transistor; wherein the first tracking transistor has electronic characteristics tracking those of a driving transistor of word-line driver, and the second tracking transistor has electronic characteristics tracking those of pass-gate transistor(s) in each cell of the RAM.

Abstract translation: 提供随机存取存储器（RAM）。 RAM包括多个字线驱动器，至少第一跟踪晶体管和第二跟踪晶体管。 每个字线驱动器具有接收解码信号的输入节点，接收操作电压的功率节点和驱动字线的驱动节点。 在一个实施例中，第一跟踪晶体管具有分别耦合到字线驱动器之一的驱动节点和第二跟踪晶体管的通道终端节点的两个通道终端节点; 其中所述第一跟踪晶体管具有跟踪字线驱动器的驱动晶体管的电子特性的电子特性，并且所述第二跟踪晶体管具有跟踪所述RAM的每个单元中的栅极晶体管的电子特性。

公开(公告)号：US20080144362A1

公开(公告)日：2008-06-19

申请号：US12040966

申请日：2008-03-03

Applicant: Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

Inventor： Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

IPC: G11C11/412

CPC classification number: G11C11/412 ,  H01L27/1104

Abstract: Techniques are provided for asymmetrical SRAM cells which can be improved, for example, by providing one or more of improved read stability and improved write performance and margin. A first inverter and a second inverter are cross-coupled and configured for selective coupling to true and complementary bit lines under control of read and write word lines. The first inverter is formed by a first, n-type, FET (NFET) and a second, p-type, FET (PFET). Process and/or technology approaches can be employed to adjust the relative strength of the FETS to obtain, for example, read margin, write margin, and/or write performance improvements.

Abstract translation: 为非对称SRAM单元提供技术，例如可通过提供改进的读取稳定性和改进的写入性能和余量来提供一个或多个。 第一反相器和第二反相器被交叉耦合并且被配置为在读和写字线的控制下选择性地耦合到真和互补的位线。 第一反相器由第一n型FET（NFET）和第二p型FET（PFET）形成。 可以采用过程和/或技术方法来调整FET的相对强度，以获得例如读取余量，写入裕度和/或写入性能改进。

公开(公告)号：US20080084733A1

公开(公告)日：2008-04-10

申请号：US11933505

申请日：2007-11-01

Applicant: Ching-Te Chuang ,  Jac-Joon Kim ,  Keunwoo Kim

Inventor： Ching-Te Chuang ,  Jac-Joon Kim ,  Keunwoo Kim

IPC: G11C11/00

CPC classification number: G11C11/412 ,  G11C11/413

Abstract: Techniques are provided for back-gate control in an asymmetrical memory cell. In one aspect, the cell includes five transistors and can be employed for static random access memory (SRAM) applications. An inventive memory circuit can include a plurality of bit line structures, a plurality of word line structures that intersect the plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at the plurality of cell locations. Each cell can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each cell can include a first inverter having first and second field effect transistors (FETS) and a second inverter with third and fourth FETS that is cross-coupled to the first inverter to form a storage flip-flop. One of the FETS in the first inverter can be configured with independent front and back gates and can function as both an access transistor and part of one of the inverters.

Abstract translation: 为非对称存储单元中的背栅极控制提供技术。 在一个方面，电池包括五个晶体管，并且可以用于静态随机存取存储器（SRAM）应用。 本发明的存储器电路可以包括多个位线结构，与多个位线结构相交以形成多个单元位置的多个字线结构以及位于多个单元位置的多个单元。 每个单元可以在对应的一个字线结构的控制下选择性地耦合到相应的一个位线结构。 每个单元可以包括具有第一和第二场效应晶体管（FETS）的第一反相器和具有与第一反相器交叉耦合以形成存储触发器的第三和第四FET的第二反相器。 第一反相器中的FETS之一可以配置有独立的前门和后门，并且可以用作存取晶体管和其中一个逆变器的一部分。

公开(公告)号：US20070040584A1

公开(公告)日：2007-02-22

申请号：US11204401

申请日：2005-08-16

Applicant: Hung Ngo ,  Ching-Te Chuang ,  Keunwoo Kim ,  Jente Kuang ,  Kevin Nowka

Inventor： Hung Ngo ,  Ching-Te Chuang ,  Keunwoo Kim ,  Jente Kuang ,  Kevin Nowka

IPC: H03K19/096

CPC classification number: H03K19/0963

Abstract: A dynamic logic gate has an asymmetrical dual-gate PFET device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node during an evaluate phase of the clock. The front gate of the asymmetrical dual-gate PFET device is coupled to the clock signal and the back gate is coupled to the ground potential of the power supply. When the clock is a logic zero both the front gate and the back gate are biased ON and the dynamic node charges with maximum current. The clock signal transitions to a logic one during the evaluation phase of the clock turning OFF the front gate. The back gate remains ON and the asymmetrical dual-gate PFET device operates as a keeper device with a current level sufficient to counter leakage on the dynamic node.

公开(公告)号：US20070018248A1

公开(公告)日：2007-01-25

申请号：US11184244

申请日：2005-07-19

Applicant: Ching-Te Chuang ,  Koushik Das ,  Shih-Hsien Lo ,  Jeffrey Sleight

Inventor： Ching-Te Chuang ,  Koushik Das ,  Shih-Hsien Lo ,  Jeffrey Sleight

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/092

Abstract: Disclosed are a multi-threshold CMOS circuit and a method of designing such a circuit. The preferred embodiment combines an MTCMOS scheme and a hybrid SOI-epitaxial CMOS structure. Generally, the logic transistors (both nFET and pFET) are placed in SOI, preferably in a high-performance, high density UTSOI; while the headers or footers are made of bulk epitaxial CMOS devices, with or without an adaptive well-biasing scheme. The logic transistors are based on (100) SOI devices or super HOT, the header devices are in bulk (100) or (110) pFETs with or without an adaptive well biasing scheme, and the footer devices are in bulk (100) NFET with or without an adaptive well biasing scheme.

Abstract translation: 公开了一种多阈值CMOS电路和一种设计这种电路的方法。 优选实施例组合MTCMOS方案和混合SOI外延CMOS结构。 通常，逻辑晶体管（nFET和pFET都）放置在SOI中，优选地以高性能，高密度的UTSOI; 而集管或页脚由大量外延CMOS器件制成，具有或不具有自适应阱偏置方案。 逻辑晶体管基于（100）SOI器件或超级HOT，头部器件处于具有或不具有自适应阱偏置方案的体（100）或（110）pFET中，并且脚踏器件处于本体（100）NFET中 或没有自适应井偏置方案。

公开(公告)号：US08854897B2

公开(公告)日：2014-10-07

申请号：US13665941

申请日：2012-11-01

Applicant: Ching-Te Chuang ,  Nan-Chun Lien ,  Wei-Nan Liao ,  Chi-Hsin Chang ,  Hao-I Yang ,  Wei Hwang ,  Ming-Hsien Tu

Inventor： Ching-Te Chuang ,  Nan-Chun Lien ,  Wei-Nan Liao ,  Chi-Hsin Chang ,  Hao-I Yang ,  Wei Hwang ,  Ming-Hsien Tu

IPC: G11C7/10

CPC classification number: G11C11/413

Abstract: A static random access memory apparatus and a bit-line voltage controller includes a controller, a pull-up circuit, a pull-down circuit and a voltage keeping circuit. The controller receives a bank selecting signal and a clock signal, and decides a pull-up time period, a pull-down time period and a voltage keeping time period according to the bank selecting signal and the clock signal. The pull-up circuit pulls up a bit-line power according to a first reference voltage within the pull-up time period. The pull-down circuit pulls down the bit-line power according to a second reference voltage within the pull-down time period. The voltage keeping circuit keeps the bit-line power to equal to an output voltage during the voltage keeping time period. The voltage keeping time period is after the pull-up time period and the pull-down time period.

Abstract translation: 静态随机存取存储装置和位线电压控制器包括控制器，上拉电路，下拉电路和保压电路。 控制器接收存储体选择信号和时钟信号，并且根据存储体选择信号和时钟信号确定上拉时间段，下拉时间段和保持时间周期。 上拉电路在上拉时间段内根据第一个参考电压拉出位线电源。 下拉电路在下拉时间段内根据第二参考电压拉低位线电源。 电压保持电路在电压保持时间段期间将位线功率保持为等于输出电压。 电压保持时间段在上拉时间段和下拉时间段之后。

公开(公告)号：US20130194861A1

公开(公告)日：2013-08-01

申请号：US13562330

申请日：2012-07-31

Applicant: Shyh-Jye Jou ,  Jhih-Yu Lin ,  Ching-Te Chuang ,  Ming-Hsien Tu ,  Yi-Wei Chiu

Inventor： Shyh-Jye Jou ,  Jhih-Yu Lin ,  Ching-Te Chuang ,  Ming-Hsien Tu ,  Yi-Wei Chiu

IPC: G11C11/00

CPC classification number: G11C11/412

Abstract: A single-ended SRAM including at least one memory cell and a third switch is provided. The memory cell includes a data-latching unit, a first switch, a second switch and a data-transferring unit. The data-latching unit is configured for latching the received input data and provides a storage data and the inverse data of the storage data. The first switch transfers a reference data to the data-latching unit according to a first word-line signal. The second switch transfers the reference data to the data-latching unit according to a second word-line signal. The data-transferring unit decides whether or not to transfer the reference data to the bit-line according to the storage data and a control signal. The third switch receives the reference data and the control signal and transfers the reference data to the first switch, the second switch and the data-transferring unit according to the control signal.

Abstract translation: 提供包括至少一个存储单元和第三开关的单端SRAM。 存储单元包括数据锁存单元，第一开关，第二开关和数据传送单元。 数据锁存单元被配置为锁存接收到的输入数据，并提供存储数据和存储数据的逆数据。 第一开关根据第一字线信号将参考数据传送到数据锁存单元。 第二开关根据第二字线信号将参考数据传送到数据锁存单元。 数据传送单元根据存储数据和控制信号决定是否将参考数据传送到位线。 第三开关接收参考数据和控制信号，并根据控制信号将参考数据传送到第一开关，第二开关和数据传送单元。

公开(公告)号：US08213257B2

公开(公告)日：2012-07-03

申请号：US12852759

申请日：2010-08-09

Applicant: Ching-Te Chuang ,  Yi-Wei Lin ,  Chia-Cheng Chen ,  Wei-Chiang Shih

Inventor： Ching-Te Chuang ,  Yi-Wei Lin ,  Chia-Cheng Chen ,  Wei-Chiang Shih

IPC: G11C8/00

CPC classification number: G11C8/08 ,  G11C11/413

Abstract: A Random Access Memory (RAM) is provided. The RAM includes a plurality of word-line drivers, at least a first tracking transistor and a second tracking transistor. Each word-line driver has an input node receiving a decoding signal, a power node receiving an operation voltage and a driving node driving a word-line. In an embodiment, the first tracking transistor has two channel terminal nodes respectively coupled to the driving node of one of the word-line driver and a channel terminal node of the second tracking transistor; wherein the first tracking transistor has electronic characteristics tracking those of a driving transistor of word-line driver, and the second tracking transistor has electronic characteristics tracking those of pass-gate transistor(s) in each cell of the RAM.

Abstract translation: 提供随机存取存储器（RAM）。 RAM包括多个字线驱动器，至少第一跟踪晶体管和第二跟踪晶体管。 每个字线驱动器具有接收解码信号的输入节点，接收操作电压的功率节点和驱动字线的驱动节点。 在一个实施例中，第一跟踪晶体管具有分别耦合到字线驱动器之一的驱动节点和第二跟踪晶体管的通道终端节点的两个通道终端节点; 其中所述第一跟踪晶体管具有跟踪字线驱动器的驱动晶体管的电子特性的电子特性，并且所述第二跟踪晶体管具有跟踪所述RAM的每个单元中的栅极晶体管的电子特性。