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59 条记录 (耗时 0.031 秒)

    Optoelectronic coupling device and method of making
    41.
    发明授权
    Optoelectronic coupling device and method of making 失效
    光电耦合器件及其制造方法

    公开(公告)号：US5309537A

    公开(公告)日：1994-05-03

    申请号：US43944

    申请日：1993-04-05

    申请人： Christopher K. Y. Chun ,  Davis H. Hartman ,  Shun-Meen Kuo ,  Michael S. Lebby

    发明人： Christopher K. Y. Chun ,  Davis H. Hartman ,  Shun-Meen Kuo ,  Michael S. Lebby

    IPC分类号： G02B6/255 ,  G02B6/122 ,  G02B6/30 ,  G02B6/42 ,  G02B6/43

    CPC分类号： G02B6/30 ,  G02B6/1221 ,  G02B6/42 ,  G02B6/423 ,  G02B6/43

    摘要： An optical electronic coupling device (100) including a molded waveguide (101, 301, 401) having a plurality of core regions (105) surrounded by a cladding region (103). Cross-sections of the core regions (105) are exposed in an opening (113, 213,313) at one end of the waveguide. An optical cable (102, 303) having a plurality of optical fibers (107, 108, 109, 300) with core regions (123, 124, 125) is inserted into the opening (113, 213, 313), thereby aligning the core regions (123, 124, 125) of the optical fibers (107, 108, 109, 300) with the exposed cross-sections (122) of the core regions (105) of the optical electronic device (100).

    摘要翻译： 一种光学电子耦合装置（100），包括具有由包层区域（103）包围的多个芯区域（105）的模制波导（101,301,401）。 芯部区域（105）的横截面在波导的一端处的开口（113,213,313）中露出。 具有多个具有芯区（123,124,125）的光纤（107,108,109,300）的光缆（102,303）被插入到所述开口（113,213,313）中，从而使所述芯 光纤（107,108,109,300）的区域（123,124,125）与光电子器件（100）的芯区域（105）的暴露的横截面（122）之间。

    Circuit having logic state retention during power-down and method therefor
    44.
    发明授权
    Circuit having logic state retention during power-down and method therefor 有权
    断电期间具有逻辑状态保持的电路及其方法

    公开(公告)号：US07619440B2

    公开(公告)日：2009-11-17

    申请号：US12022199

    申请日：2008-01-30

    申请人： Robert J. Amedeo ,  Christopher K. Y. Chun

    发明人： Robert J. Amedeo ,  Christopher K. Y. Chun

    IPC分类号： H03K17/16 ,  H03K19/003

    CPC分类号： H03K19/0016

    摘要： A storage circuit has an input for receiving and storing data, a first power terminal coupled to a first conductor for receiving a first power supply voltage, and a second power terminal coupled to a second conductor. A power gate device has a first terminal coupled to the second conductor, a control terminal for receiving a bias voltage in response to a control signal, and a second terminal coupled to a terminal for receiving a second power supply voltage. A shorting device selectively electrically short circuits the first terminal of the power gate device to the control terminal of the power gate device in response to the control signal, thereby converting the power gate device from a transistor into a diode-connected device. The shorting device is smaller in size than the power gate device.

    摘要翻译： 存储电路具有用于接收和存储数据的输入端，耦合到用于接收第一电源电压的第一导体的第一电源端子和耦合到第二导体的第二电源端子。 功率门装置具有耦合到第二导体的第一端子，用于响应于控制信号接收偏置电压的控制端子，以及耦合到端子的用于接收第二电源电压的第二端子。 短路装置响应于控制信号选择性地将电力门装置的第一端子短路到电力门装置的控制端子，从而将电源栅极装置从晶体管转换成二极管连接的装置。 短路装置的尺寸小于电源门装置。

    Power management system
    45.
    发明授权
    Power management system 有权
    电源管理系统

    公开(公告)号：US07608942B2

    公开(公告)日：2009-10-27

    申请号：US10542669

    申请日：2003-01-17

    申请人： Christopher K. Y. Chun ,  Cornelis H. Voorwinden

    发明人： Christopher K. Y. Chun ,  Cornelis H. Voorwinden

    IPC分类号： H02J1/00 ,  H02M3/02 ,  H05K1/02

    CPC分类号： G05F1/56 ,  Y10T307/352 ,  Y10T307/391 ,  Y10T307/469 ,  Y10T307/492

    摘要： An integrated circuit (103) having a plurality of integrated circuit portions (111, 113, and 115) where each of the plurality of integrated circuit portions receives a corresponding voltage of a plurality of voltages. Selection circuitry (127 and 123) selects a selected voltage of the plurality of voltages and provides an indication of the selected voltage to adjust the supply voltage to the integrated circuit. in one embodiment, the indication may correspond to an analog signal proportional to the selected voltage such as e.g. at the selected voltage or at a voltage less than or greater than the selected voltage. A power supply system (105), coupled to the integrated circuit, may be used to receive the indication of the selected voltage and adjust the supply voltage based on the indication.

    摘要翻译： 一种具有多个集成电路部分（111,113和115）的集成电路（103），其中多个集成电路部分中的每一个接收多个电压的对应电压。 选择电路（127和123）选择多个电压的选定电压，并提供所选电压的指示以调整对集成电路的电源电压。 在一个实施例中，该指示可以对应于与所选择的电压成比例的模拟信号，例如。 在所选择的电压或小于或大于所选电压的电压。 耦合到集成电路的电源系统（105）可以用于接收所选择的电压的指示并且基于该指示来调节电源电压。

    State retention within a data processing system
    46.
    发明授权
    State retention within a data processing system 有权
    在数据处理系统中保留状态

    公开(公告)号：US07183825B2

    公开(公告)日：2007-02-27

    申请号：US10818861

    申请日：2004-04-06

    申请人： Milind P. Padhye ,  Christopher K. Y. Chun ,  Yuan Yuan ,  Sanjay Gupta

    发明人： Milind P. Padhye ,  Christopher K. Y. Chun ,  Yuan Yuan ,  Sanjay Gupta

    IPC分类号： H03K3/289

    CPC分类号： G11C5/147

    摘要： Power consumption may be reduced through the use of power gating in which power is removed from circuit blocks or portions of circuit blocks in order to reduce leakage current. One embodiment uses a modified state retention flip-flop capable of retaining state when power is removed or partially removed from the circuit. Another embodiment uses a modified state retention buffer capable of retaining state when power is removed or partially removed from the circuit. The state retention flip-flop and buffer may be used to allow for state retention while still reducing leakage current. Also disclosed are various methods of reducing power and retaining state using, for example, the state retention flip-flops and buffers. For example, software, hardware, or a combination of software and hardware methods may be used to enter a deep sleep or idle mode while retaining state.

    摘要翻译： 通过使用从电路块或电路块的一部分去除功率的功率门控，可以降低功耗，以减少漏电流。 一个实施例使用修改的状态保持触发器，其能够在电力被去除或部分地从电路中移除时保持状态。 另一实施例使用修改状态保持缓冲器，其能够在电力被去除或部分地从电路中移除时保持状态。 状态保持触发器和缓冲器可以用于允许状态保持同时仍然减少漏电流。 还公开了使用例如状态保持触发器和缓冲器来降低功率和保持状态的各种方法。 例如，软件，硬件或软件和硬件方法的组合可以用于在保持状态的同时进入深度睡眠或空闲模式。

    Integrated circuit well bias circuity
    47.
    发明授权
    Integrated circuit well bias circuity 有权
    集成电路阱偏置电路

    公开(公告)号：US06927429B2

    公开(公告)日：2005-08-09

    申请号：US10366842

    申请日：2003-02-14

    申请人： Christopher K. Y. Chun ,  Der Yi Sheu

    发明人： Christopher K. Y. Chun ,  Der Yi Sheu

    IPC分类号： H01L27/02 ,  H01L27/10 ,  H03K19/00

    CPC分类号： H01L27/0203 ,  H03K19/0016

    摘要： Well bias circuitry for selectively biasing the voltages of the well areas of an integrated circuit. In one embodiment, the well bias circuitry includes a switching cell located in a row of cells of the integrated circuit for selectively coupling a voltage supply line to a well bias line. The switching cell may include two level shifters, each for providing a voltage to a gate of a coupling transistor to make the coupling transistor non conductive in response to an enable signal. The switching cells may be sequentially coupled such that the coupling transistors of each of the switching cells are not made conductive at the same time so as to reduce inrush current due to changing the well bias from a well bias voltage to a supply voltage. In one example, the switching cells may include delay circuitry for delaying the change in state of the enable signal before being provided to the next switching cell.

    摘要翻译： 用于选择性地偏置集成电路的阱区域的电压的良好偏置电路。 在一个实施例中，阱偏置电路包括位于集成电路的一行单元中的开关单元，用于选择性地将电压供应线耦合到阱偏置线。 开关单元可以包括两个电平移位器，每个电平移位器用于向耦合晶体管的栅极提供电压，以使得耦合晶体管响应于使能信号而不导通。 开关单元可以顺序耦合，使得每个开关单元的耦合晶体管不会同时导通，以便由于将阱偏压从阱偏置电压改变到电源电压来减少浪涌电流。 在一个示例中，开关单元可以包括延迟电路，用于在提供给下一个开关单元之前延迟使能信号的状态的改变。

    Circuit and method of encoding and decoding digital data transmitted along optical fibers
    50.
    发明授权
    Circuit and method of encoding and decoding digital data transmitted along optical fibers 失效
    对沿光纤传输的数字数据进行编码和解码的电路和方法

    公开(公告)号：US5673130A

    公开(公告)日：1997-09-30

    申请号：US582841

    申请日：1996-01-02

    申请人： Ray D. Sundstrom ,  Daniel B. Schwartz ,  Christopher K. Y. Chun ,  Stephen G. Shook

    发明人： Ray D. Sundstrom ,  Daniel B. Schwartz ,  Christopher K. Y. Chun ,  Stephen G. Shook

    IPC分类号： H03M5/04 ,  H04B10/02 ,  H04B10/12 ,  H04B10/18 ,  H04L7/00 ,  H04L25/06 ,  H04L25/49 ,  H04B10/00

    CPC分类号： H04B10/516 ,  H04L25/062 ,  H04L7/0008 ,  H04L7/0075

    摘要： A data transmitter (12) transmits parallel data as light pulses over multiple optical channels (14). A data receiver (16) converts the light pulses back to a voltage level and compares the voltage level to a reference capacitor voltage (42). The capacitor voltage should maintain a mid-range value for proper noise margin in detecting logic ones and logic zeroes. Any long series of consecutive logic ones or zeroes causes the capacitor voltage to charge or discharge toward the same level as the data voltage, which causes data errors. To prevent the data errors, the data is encoded (18) by inverting certain bits to break up the long series of consecutive logic states. The encoding information is transmitted as a transmitted clock to the data receiver over another fiber optic channel. The decoding information is retrieved (20) so that the encoded data can be converted back to proper logic states.

    摘要翻译： 数据发送器（12）将并行数据作为光脉冲发送在多个光通道（14）上。 数据接收器（16）将光脉冲转换回电压电平，并将电压电平与参考电容器电压（42）进行比较。 在检测逻辑和逻辑零时，电容电压应保持适当的噪声容限的中档值。 任何长串连续的逻辑或零都会使电容器电压与数据电压相同的电平进行充放电，从而导致数据错误。 为了防止数据错误，通过反转某些位来对数据进行编码（18）以分解长序列的连续逻辑状态。 编码信息作为发送时钟通过另一个光纤信道被发送到数据接收器。 检索解码信息（20），使得编码数据可被转换回适当的逻辑状态。