公开(公告)号：US06214679B1

公开(公告)日：2001-04-10

申请号：US09476393

申请日：1999-12-30

申请人： Anand Murthy ,  Robert S. Chau

发明人： Anand Murthy ,  Robert S. Chau

IPC分类号： H01L21336

CPC分类号： H01L29/66636 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/28562 ,  H01L29/045 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/4941 ,  H01L29/665

摘要： A method of forming a cobalt germanosilicide film is described. According to the present invention a silicon germanium alloy is formed on a substrate. A cobalt film is then formed on the silicon germanium alloy. The substrate is then heated to a temperature of greater than 850° C. for a period of time less than 20 seconds to form a cobalt germanium silicide film.

摘要翻译： 描述形成锗硅酸钴膜的方法。 根据本发明，在基板上形成硅锗合金。 然后在硅锗合金上形成钴膜。 然后将衬底加热至大于850℃的温度一段时间少于20秒以形成锗化锗硅化物膜。

公开(公告)号：US20110186912A1

公开(公告)日：2011-08-04

申请号：US13082305

申请日：2011-04-07

申请人： Anand Murthy ,  Boyan Boyanov ,  Suman Datta ,  Brian S. Doyle ,  Been-Yih Jin ,  Shaofeng Yu ,  Robert Chau

发明人： Anand Murthy ,  Boyan Boyanov ,  Suman Datta ,  Brian S. Doyle ,  Been-Yih Jin ,  Shaofeng Yu ,  Robert Chau

IPC分类号： H01L29/772 ,  H01L27/092

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848

摘要： Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.

摘要翻译： 本发明的各种实施例涉及在衬底上具有硅锗材料的晶体管沟道的PMOS器件，介电常数大于沟道上的二氧化硅的介电常数的栅极电介质，具有功函数的栅电极导体材料 在栅极电介质上的硅的价态能带边缘和导体能带边缘之间的范围，以及栅电极导体材料上的栅电极半导体材料。

公开(公告)号：US20110018031A1

公开(公告)日：2011-01-27

申请号：US12893983

申请日：2010-09-29

申请人： Anand Murthy ,  Boyan Boyanov ,  Suman Datta ,  Brian S. Doyle ,  Been-Yih Jin ,  Shaofeng Yu ,  Robert Chau

发明人： Anand Murthy ,  Boyan Boyanov ,  Suman Datta ,  Brian S. Doyle ,  Been-Yih Jin ,  Shaofeng Yu ,  Robert Chau

IPC分类号： H01L29/78

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848

摘要： Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.

公开(公告)号：US07812394B2

公开(公告)日：2010-10-12

申请号：US12250191

申请日：2008-10-13

申请人： Anand Murthy ,  Glenn A. Glass ,  Andrew N. Westmeyer ,  Michael L. Hattendorf ,  Jeffrey R. Wank

发明人： Anand Murthy ,  Glenn A. Glass ,  Andrew N. Westmeyer ,  Michael L. Hattendorf ,  Jeffrey R. Wank

IPC分类号： H01L31/119

CPC分类号： H01L29/7848 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/517 ,  H01L29/66628 ,  H01L29/7834

摘要： This invention adds to the art of replacement source-drain cMOS transistors. Processes may involve etching a recess in the substrate material using one equipment set, then performing deposition in another. Disclosed is a method to perform the etch and subsequent deposition in the same reactor without atmospheric exposure. In-situ etching of the source-drain recess for replacement source-drain applications provides several advantages over state of the art ex-situ etching. Transistor drive current is improved by: (1) Eliminating contamination of the silicon-epilayer interface when the as-etched surface is exposed to atmosphere and (2) Precise control over the shape of the etch recess. Deposition may be done by a variety of techniques including selective and non-selective methods. In the case of blanket deposition, a measure to avoid amorphous deposition in performance critical regions is also presented.

摘要翻译： 本发明增加了替代源极 - 漏极cMOS晶体管的技术。 方法可以包括使用一个设备组来蚀刻衬底材料中的凹部，然后在另一个设备组中进行沉积。 公开了一种在没有大气暴露的情况下在相同的反应器中进行蚀刻和随后的沉积的方法。 用于替代源极 - 漏极应用的源极 - 漏极凹槽的原位蚀刻提供了优于现有技术的非原位蚀刻的几个优点。 晶体管驱动电流通过以下因素得到改善：（1）当被蚀刻的表面暴露于大气中时，消除硅 - 外延层界面的污染，（2）精确控制蚀刻凹槽的形状。 沉积可以通过各种技术进行，包括选择性和非选择性方法。 在覆盖层沉积的情况下，还提出了避免在性能关键区域中无定形沉积的措施。

公开(公告)号：US07517768B2

公开(公告)日：2009-04-14

申请号：US10404781

申请日：2003-03-31

申请人： Ravindra Soman ,  Anand Murthy ,  Peter VanDerVoorn ,  Shahriar Ahmed

发明人： Ravindra Soman ,  Anand Murthy ,  Peter VanDerVoorn ,  Shahriar Ahmed

IPC分类号： H01L21/331

CPC分类号： H01L29/66242

摘要： A bipolar transistor with a SiGe:C film and a seed layer forming beneath the SiGe:C film and methods of making same. The method includes placing a substrate in a reactor chamber and introducing a silicon source gas into the reactor chamber to form a silicon seed layer. The reactor chamber is maintained at a pressure below 45 Torr and a temperature between about 700° C. and 850° C. After the seed layer is formed, the silicon source gas is stopped. The reactor chamber is then simultaneously adjusted to a pressure between about 70 Torr and 90 Torr and a temperature between about 600° C. and 650° C. The silicon source gas, a germanium source gas, and a carbon source gas are introduced to form the SiGe:C film on the seed layer.

摘要翻译： 具有SiGe：C膜的双极晶体管和形成在SiGe：C薄膜下面的晶种层及其制造方法。 该方法包括将基板放置在反应器室中并将硅源气体引入反应器室以形成硅籽晶层。 反应室保持在低于45托的压力和约700℃至850℃之间的温度。形成种子层之后，停止硅源气体。 然后将反应器室同时调节至约70托和90托之间的压力以及约600℃和650℃之间的温度。引入硅源气体，锗源气体和碳源气体以形成 种子层上的SiGe：C膜。

公开(公告)号：US07473947B2

公开(公告)日：2009-01-06

申请号：US10194506

申请日：2002-07-12

申请人： Anand Murthy ,  Brian Doyle ,  Jack Kavalieros ,  Robert Chau

发明人： Anand Murthy ,  Brian Doyle ,  Jack Kavalieros ,  Robert Chau

IPC分类号： H01L21/00

CPC分类号： H01L29/41733 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78618

摘要： The invention relates to a transistor that includes an ultra-thin body epitaxial layer that forms an embedded junction with a channel that has a length dictated by an undercut under the gate stack for the transistor. The invention also relates to a process of forming the transistor and to a system that incorporates the transistor.

摘要翻译： 本发明涉及一种晶体管，其包括超薄体外延层，该超薄体外延层与具有由晶体管的栅极堆叠下方的底切指定的沟道的沟道形成嵌入的结。 本发明还涉及一种形成晶体管的方法以及结合晶体管的系统。

公开(公告)号：US07364976B2

公开(公告)日：2008-04-29

申请号：US11387012

申请日：2006-03-21

申请人： Willy Rachmady ,  Anand Murthy

发明人： Willy Rachmady ,  Anand Murthy

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/32134 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636

摘要： A method to selectively etch, and hence pattern, a semiconductor film deposited non-selectively is described. In one embodiment, a carbon-doped silicon film is deposited non-selectively such that the film forms an epitaxial region where deposited on a crystalline surface and an amorphous region where deposited on an amorphous surface. A four-component wet etch mixture is tuned to selectively etch the amorphous region while retaining the epitaxial region, wherein the four-component wet etch mixture comprises an oxidizing agent, an etchant, a buffer and a diluent.

摘要翻译： 描述了非选择性地沉积半导体膜并因此图案化的方法。 在一个实施例中，碳掺杂硅膜被非选择性地沉积，使得膜形成沉积在沉积在非晶表面上的结晶表面和非晶区域上的外延区域。 调节四组分湿蚀刻混合物以选择性地蚀刻非晶区域同时保留外延区域，其中四组分湿蚀刻混合物包含氧化剂，蚀刻剂，缓冲剂和稀释剂。

公开(公告)号：US20080044968A1

公开(公告)日：2008-02-21

申请号：US11899881

申请日：2007-09-07

申请人： Anand Murthy ,  Boyan Boyanov ,  Glenn Glass ,  Thomas Hoffmann

发明人： Anand Murthy ,  Boyan Boyanov ,  Glenn Glass ,  Thomas Hoffmann

IPC分类号： H01L21/8238

CPC分类号： H01L29/7848 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41725 ,  H01L29/6628 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7842 ,  Y10S438/933

摘要： An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.

摘要翻译： 本发明的一个实施例通过利用用于源极和漏极区域的硅锗合金和镍硅锗自对准硅化物（即，自对准硅化物）层来形成源极和漏极区域的接触表面来降低晶体管的外部电阻 。 基于硅锗和硅化物之间的金属半导体功函数降低，硅锗与硅硅锗硅的界面具有较低的比接触电阻率，并且硅锗与硅中的载流子迁移率增加。 可以掺杂硅锗以进一步调整其电性能。 降低晶体管的外部电阻等同于在开关速度和功耗方面提高晶体管的性能。

公开(公告)号：US20070194391A1

公开(公告)日：2007-08-23

申请号：US11789338

申请日：2007-04-24

申请人： Anand Murthy ,  Justin Brask ,  Andrew Westmeyer ,  Boyan Boyanov ,  Nick Lindert

发明人： Anand Murthy ,  Justin Brask ,  Andrew Westmeyer ,  Boyan Boyanov ,  Nick Lindert

IPC分类号： H01L29/76

CPC分类号： H01L29/0847 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： The mobility of carriers may be increased in strained channel epitaxial source/drain transistors. Doped silicon material may be blanket deposited after removing ion implanted source/drain regions. The blanket deposition forms amorphous films over non-source/drain areas and crystalline films in source/drain regions. By using an etch which is selective to amorphous silicon, the amorphous material may be removed. This may avoid some problems associated with selective deposition of the doped silicon material.

公开(公告)号：US07202514B2

公开(公告)日：2007-04-10

申请号：US10418395

申请日：2003-04-17

申请人： Shahriar Ahmed ,  Mark Bohr ,  Stephen Chambers ,  Richard Green ,  Anand Murthy

发明人： Shahriar Ahmed ,  Mark Bohr ,  Stephen Chambers ,  Richard Green ,  Anand Murthy

IPC分类号： H01L31/072

CPC分类号： H01L29/66287

摘要： The invention relates to a process of forming a bipolar junction transistor (BJT) that includes forming a topology over a substrate. Thereafter, a spacer is formed at the topology. A base layer is formed from epitaxial silicon above the spacer and at the topology. A leakage block structure is formed in the substrate by out-diffusion from the spacer. Thereafter a BJT is completed with the base layer and the spacer.

摘要翻译： 本发明涉及一种形成双极结型晶体管（BJT）的方法，其包括在衬底上形成拓扑结构。 此后，在拓扑形成间隔物。 基底层由间隔物上方的外延硅和拓扑形成。 通过从间隔物的扩散形成在衬底中的泄漏块结构。 此后，BJT完成了基层和隔离层。