公开(公告)号：US20060015283A1

公开(公告)日：2006-01-19

申请号：US10891759

申请日：2004-07-15

申请人： David Boerstler ,  Eskinder Hailu

发明人： David Boerstler ,  Eskinder Hailu

IPC分类号： G01R27/28

CPC分类号： G01R31/2882

摘要： The present invention provides for determining gate speed parameters in a circuit. A first delay is selected. A second delay is selected, wherein the second delay is longer than the first delay. A clock signal is delayed as a function of the first delay. The clock signal is combined with the first delayed clock signal. A first pulse signal is produced from combining the clock signal with the first delayed clock signal. A clock signal is delayed as a function of the second delay. The clock signal is combined with the first delayed clock signal. A second pulse signal is produced from combining the clock signal with the second delayed clock signal. The first delayed clock signal is integrated. The second delayed clock signal is integrated. The first delayed integrated clock signal is compared with the second delayed integrated clock signal. When the first delayed integrated clock signal is greater than the second integrated clock signal, the gate delay is determined.

摘要翻译： 本发明提供了确定电路中的门速度参数。 选择第一个延迟。 选择第二延迟，其中第二延迟长于第一延迟。 时钟信号作为第一延迟的函数被延迟。 时钟信号与第一延迟时钟信号组合。 通过将时钟信号与第一延迟时钟信号组合来产生第一脉冲信号。 时钟信号作为第二延迟的函数被延迟。 时钟信号与第一延迟时钟信号组合。 通过将时钟信号与第二延迟时钟信号组合来产生第二脉冲信号。 第一个延迟时钟信号被集成。 第二个延迟时钟信号被集成。 将第一延迟积分时钟信号与第二延迟积分时钟信号进行比较。 当第一延迟积分时钟信号大于第二集成时钟信号时，确定门延迟。

公开(公告)号：US20050248412A1

公开(公告)日：2005-11-10

申请号：US10840561

申请日：2004-05-06

申请人： David Boerstler ,  Eskinder Hailu

发明人： David Boerstler ,  Eskinder Hailu

IPC分类号： H03L7/00 ,  H03L7/06 ,  H03L7/089 ,  H03L7/093

CPC分类号： H03L7/0891 ,  H03L7/093

摘要： The present invention provides for a phased locked loop. A capacitor has an associated leakage current. A differential circuit is coupled to the capacitor of a low pass filter. A voltage follower circuit is coupled to the output of the differential circuit. The gate of a field effect transistor (FET) is coupled to an output of the voltage follower circuit. A current mirror is coupled to the FET, the current mirror having a first source and a second source, wherein the second current mirror source is coupled to the drain of the FET, wherein an output of the first current mirror source is coupled to the capacitor. Through the employment of current mirror source, leakage charge within the capacitor is replaced.

摘要翻译： 本发明提供了一种定相锁相环。 电容器具有相关的漏电流。 差分电路耦合到低通滤波器的电容器。 电压跟随器电路耦合到差分电路的输出。 场效应晶体管（FET）的栅极耦合到电压跟随器电路的输出端。 电流镜耦合到FET，电流镜具有第一源极和第二源极，其中第二电流镜源耦合到FET的漏极，其中第一电流镜源的输出耦合到电容器 。 通过使用电流镜源，更换电容器内的漏电。

公开(公告)号：US20050213699A1

公开(公告)日：2005-09-29

申请号：US10809592

申请日：2004-03-25

申请人： David Boerstler ,  Eskinder Hailu ,  Eric Lukes

发明人： David Boerstler ,  Eskinder Hailu ,  Eric Lukes

IPC分类号： H03K5/1252 ,  H03K21/00 ,  H03K23/66

CPC分类号： H03K23/667 ,  H03K5/1252

摘要： The present invention provides for a divider circuit for reducing anomalous output timing pulses. A latch is coupled to the division selection line. A comparator is coupled to the division selection line. A first synchronizer coupled to the output of the latch. A frequency divider is coupled to the output of the synchronizer. A second synchronizer is coupled to the output of the comparator and the output of the frequency divider. There is feedback between the output of the second synchronizer and the enable input of the latch, the reset of the first synchronizer, the reset of the second synchronized, and the reset of the divide by n divider.

摘要翻译： 本发明提供一种用于减少异常输出定时脉冲的分频器电路。 锁存器耦合到分割选择线。 比较器耦合到分割选择线。 耦合到锁存器的输出的第一同步器。 分频器耦合到同步器的输出端。 第二同步器耦合到比较器的输出端和分频器的输出端。 在第二同步器的输出和锁存器的使能输入之间存在反馈，第一同步器的复位，第二同步的复位以及除法的复位除以分频器。

公开(公告)号：US20050156655A1

公开(公告)日：2005-07-21

申请号：US10759940

申请日：2004-01-16

申请人： David Boerstler ,  Eskinder Hailu

发明人： David Boerstler ,  Eskinder Hailu

IPC分类号： H03K17/16

CPC分类号： H03K17/161

摘要： A method, apparatus, and computer program are provided for correcting the voltage across a thin oxide Complementary Metal-Oxide Semiconductor (CMOS) capacitor. Due to ever-decreasing thicknesses of capacitors in CMOS applications, leakage through the capacitor by electron tunneling and impurities has become a significant problem. For example, in Phased Lock Loops (PLLs), leaky capacitors can cause static phase errors. To combat the problem, a scaled capacitor and current mirrors are used to provide a correction current to a leaky capacitor to maintain a proper voltages.

摘要翻译： 提供了一种用于校正薄氧化物互补金属氧化物半导体（CMOS）电容器两端的电压的方法，装置和计算机程序。 由于CMOS应用中电容器的厚度不断减小，通过电子隧道和杂质的电容器泄漏已成为一个重大问题。 例如，在锁相环（PLL）中，漏电容会引起静态相位错误。 为了解决这个问题，使用了一个缩放电容器和电流镜来向漏电容器提供校正电流，以保持适当的电压。

公开(公告)号：US20050129071A1

公开(公告)日：2005-06-16

申请号：US10733694

申请日：2003-12-11

申请人： David Boerstler ,  Eskinder Hailu ,  H. Hofstee

发明人： David Boerstler ,  Eskinder Hailu ,  H. Hofstee

IPC分类号： G06F13/42 ,  G06F1/08 ,  H04J3/00 ,  H04L7/00 ,  H04J3/04

CPC分类号： H04L7/0083 ,  G06F1/08

摘要： In a first aspect, a first method is provided that includes providing a plurality of select signals and a plurality of input signals for input by a multiplexer. Each select signal is adapted to cause the multiplexer to select a different one of the plurality of input signals for output by the multiplexer when the select signal is in a first logic state. The first method further includes preventing a first of the select signals that is in the first logic state from being provided to the multiplexer until the other select signals are in a second logic state. Numerous other aspects are provided.

摘要翻译： 在第一方面，提供了一种第一方法，其包括提供多个选择信号和多个输入信号以供多路复用器输入。 当选择信号处于第一逻辑状态时，每个选择信号适于使多路复用器选择多个输入信号中的不同的一个以供多路复用器输出。 第一种方法还包括防止处于第一逻辑状态的第一选择信号被提供给多路复用器，直到其他选择信号处于第二逻辑状态。 提供了许多其他方面。

公开(公告)号：US08037431B2

公开(公告)日：2011-10-11

申请号：US12126076

申请日：2008-05-23

申请人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi ,  Mike Shen

发明人： David W. Boerstler ,  Eskinder Hailu ,  Jieming Qi ,  Mike Shen

IPC分类号： G06F17/50 ,  H03K3/03

CPC分类号： H03L7/0995 ,  H03K3/0315 ,  H03K5/133

摘要： A design structure embodied in a machine readable medium used in a design process includes an interleaved voltage-controlled oscillator, including a ring circuit of main logic inverter gates; a plurality of delay elements connected in parallel with a selected sequence of the main logic inverter gates; wherein each delay element comprises a feedforward section, comprising controls for regulating signal transmission through feedforward elements responsive to one or more control voltages; and a proportional section for regulating signal transmission through at least one logic inverter gate; at least one temperature compensation circuit responsive to a compensating voltage input that is proportional to temperature; an electronic circuit in communication with the temperature compensation circuit and configured to provide a voltage signal responsive to temperature; an amplifier in connection with the electronic circuit to amplify the voltage signal; and a DC offset generator configured to adjust the voltage of the amplified voltage signal.

摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构包括交错压控振荡器，包括主逻辑逆变器门的环形电路; 多个延迟元件，与所述主逻辑反相器门的选定序列并联连接; 其中每个延迟元件包括前馈部分，其包括用于响应于一个或多个控制电压来调节通过前馈元件的信号传输的控制; 以及用于调节通过至少一个逻辑反相器门的信号传输的比例部分; 响应于与温度成比例的补偿电压输入的至少一个温度补偿电路; 与所述温度补偿电路通信并且被配置为提供响应于温度的电压信号的电子电路; 与电子电路相连的放大器，用于放大电压信号; 以及配置成调整放大的电压信号的电压的DC偏移发生器。

公开(公告)号：US07747892B2

公开(公告)日：2010-06-29

申请号：US12036936

申请日：2008-02-25

申请人： David William Boerstler ,  Eskinder Hailu ,  Kazuhiko Miki ,  Jieming Qi

发明人： David William Boerstler ,  Eskinder Hailu ,  Kazuhiko Miki ,  Jieming Qi

IPC分类号： G06F1/04

CPC分类号： H03K19/017581 ,  H03K19/00323 ,  H03K19/00346

摘要： The present invention provides for a system comprising a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a plurality of intermediate voltages in response to the received counter signal, and to generate a second clock signal in response to the received first clock signal and the selected intermediate voltage. A counter is coupled to the level shifter and configured to receive a divided clock signal and a comparison result signal, and to generate the counter signal in response to the received divided clock signal and comparison result signal. A divider is coupled to the counter and configured to receive the first clock signal and to generate the divided clock signal in response to the received first clock signal. A filter is coupled to the level shifter and configured to receive the second clock signal and to generate a first comparison signal in response to the received second clock signal. A fixed potential is configured to generate a second comparison signal. A comparator is coupled to the filter, the fixed potential, and the counter and configured to receive the first comparison signal and the second comparison signal, and to generate the comparison result signal in response to the received first comparison signal and the second comparison signal.

摘要翻译： 本发明提供了一种系统，包括电平移位器，其被配置为从第一功率域接收第一时钟信号，以接收计数器信号，以响应于所接收的计数器信号选择多个中间电压中的一个，并产生 响应于所接收的第一时钟信号和所选择的中间电压的第二时钟信号。 计数器耦合到电平移位器并被配置为接收分频时钟信号和比较结果信号，并且响应于接收到的分频时钟信号和比较结果信号产生计数器信号。 分频器耦合到计数器并且被配置为接收第一时钟信号并响应于接收到的第一时钟信号产生分频时钟信号。 滤波器耦合到电平移位器并且被配置为接收第二时钟信号并响应于所接收的第二时钟信号产生第一比较信号。 固定电位被配置为产生第二比较信号。 比较器耦合到滤波器，固定电位和计数器，并且被配置为接收第一比较信号和第二比较信号，并且响应于接收的第一比较信号和第二比较信号产生比较结果信号。

公开(公告)号：US07716516B2

公开(公告)日：2010-05-11

申请号：US11471819

申请日：2006-06-21

申请人： Yosuke Muraki ,  Tetsuji Tamura ,  Iwao Takiguchi ,  Makoto Aikawa ,  Eskinder Hailu ,  Byron Lee Krauter ,  Stephen Douglas Weitzel ,  Jieming Qi ,  Kazuhiko Miki ,  David William Boerstler ,  Gilles Gervais ,  Kirk David Peterson ,  Robert Walter Berry, Jr. ,  Sang Hoo Dhong

发明人： Yosuke Muraki ,  Tetsuji Tamura ,  Iwao Takiguchi ,  Makoto Aikawa ,  Eskinder Hailu ,  Byron Lee Krauter ,  Stephen Douglas Weitzel ,  Jieming Qi ,  Kazuhiko Miki ,  David William Boerstler ,  Gilles Gervais ,  Kirk David Peterson ,  Robert Walter Berry, Jr. ,  Sang Hoo Dhong

IPC分类号： G06F1/04 ,  G06F1/24 ,  G06F11/00

CPC分类号： G06F1/04

摘要： A technology for supplying a power supply voltage to a microprocessor. Before normal arithmetic processing of the microprocessor, duty cycle correction process for adjusting the duty cycle of a clock signal inside the microprocessor is performed. In the duty cycle correction process for adjusting the duty cycle, the duty cycle of the clock signal is adjusted so as to minimize the power voltage at which the microprocessor is still operable.

摘要翻译： 用于向微处理器提供电源电压的技术。 在微处理器的正常运算处理之前，执行用于调整微处理器内的时钟信号占空比的占空比校正处理。 在用于调整占空比的占空比校正处理中，调整时钟信号的占空比以使微处理器仍然可操作的电源电压最小化。

公开(公告)号：US07679408B2

公开(公告)日：2010-03-16

申请号：US11960832

申请日：2007-12-20

申请人： Eskinder Hailu ,  Takeo Yasuda

发明人： Eskinder Hailu ,  Takeo Yasuda

IPC分类号： G06F1/08

CPC分类号： H03K17/005 ,  G06F1/08

摘要： A circuit for switching clock signals with logic devices using a glitchless clock multiplexer optimized for synchronous and asynchronous clocks. The circuit comprises an asynchronous clock group and one or more synchronous clock group(s). The asynchronous group comprises a plurality of high frequency glitchless control (HFGC) blocks for asynchronous clock sources. Each synchronous group comprises a plurality of HFGC blocks for synchronous clock sources. The circuit comprises a multiplexer for receiving delayed input clock signals from HFGC blocks for asynchronous clock sources and from HFGC blocks for synchronous clock sources. A switching latency from a first input clock signal belonging to a synchronous group to a second input clock signal belonging to the same synchronous group is one clock cycle or less of the second input clock signal. Switching latency is the period in which no clock pulse appears at the final output of the circuit.

摘要翻译： 用于使用针对同步和异步时钟优化的无毛刺时钟复用器的逻辑器件来切换时钟信号的电路。 该电路包括异步时钟组和一个或多个同步时钟组。 异步组包括用于异步时钟源的多个高频无毛刺控制（HFGC）块。 每个同步组包括用于同步时钟源的多个HFGC块。 该电路包括用于从用于异步时钟源的HFGC块和用于同步时钟源的HFGC块接收延迟的输入时钟信号的多路复用器。 属于同步组的第一输入时钟信号与属于同一同步组的第二输入时钟信号的切换等待时间是第二输入时钟信号的一个时钟周期。 切换延迟是在电路的最终输出处没有出现时钟脉冲的周期。

公开(公告)号：US07615788B2

公开(公告)日：2009-11-10

申请号：US11699713

申请日：2007-01-29

申请人： Kevin Kornegay ,  Andrew R. Atwell ,  Mihaela Balseanu ,  Jon Duster ,  Eskinder Hailu ,  Ce Li

发明人： Kevin Kornegay ,  Andrew R. Atwell ,  Mihaela Balseanu ,  Jon Duster ,  Eskinder Hailu ,  Ce Li

IPC分类号： H01L29/84

CPC分类号： B81C1/00246 ,  B81C2203/0735

摘要： A device and method of forming electronics and microelectromechanical on a silicon carbide substrate having a slow etch rate is performed by forming circuitry on the substrate. A protective layer is formed over the circuitry having a slower etch rate than the etch rate of the silicon carbide substrate. Microelectromechanical structures supported by the substrate are then formed. The circuitry comprises a field effect transistor in one embodiment, and the protective layer comprises a heavy metal layer.

摘要翻译： 通过在衬底上形成电路来执行在具有缓蚀刻速率的碳化硅衬底上形成电子学和微机电的器件和方法。 在具有比碳化硅衬底的蚀刻速率更慢的蚀刻速率的电路上形成保护层。 然后形成由基板支撑的微机电结构。 在一个实施例中，电路包括场效应晶体管，保护层包括重金属层。