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    Magnetoresistive stack, seed region thereof and method of manufacturing same
    44.
    发明授权
    Magnetoresistive stack, seed region thereof and method of manufacturing same 有权

    公开(公告)号：US10141498B2

    公开(公告)日：2018-11-27

    申请号：US15373880

    申请日：2016-12-09

    Applicant: Everspin Technologies, Inc.

    Inventor： Renu Whig ,  Jon M. Slaughter ,  Han-Jong Chia

    IPC: H01L29/82 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

    Abstract: A magnetoresistive stack/structure and method of manufacturing same comprising wherein the stack/structure includes a seed region, a fixed magnetic region disposed on and in contact with the seed region, a dielectric layer(s) disposed on the fixed magnetic region and a free magnetic region disposed on the dielectric layer(s). In one embodiment, the seed region comprises an alloy including nickel and chromium having (i) a thickness greater than or equal to 40 Angstroms (+/−10%) and less than or equal to 60 Angstroms (+/−10%), and (ii) a material composition or content of chromium within a range of 25-60 atomic percent (+/−10%) or 30-50 atomic percent (+/−10%).

    Magnetic field sensor
    46.
    发明授权
    Magnetic field sensor 有权

    公开(公告)号：US09640753B2

    公开(公告)日：2017-05-02

    申请号：US14168095

    申请日：2014-01-30

    Applicant: EVERSPIN TECHNOLOGIES, INC.

    Inventor： Jijun Sun ,  Phillip Mather ,  Srinivas Pietambaram ,  Jon Slaughter ,  Renu Whig ,  Nicholas Rizzo

    IPC: G01R33/06 ,  H01L43/10 ,  G01R33/09 ,  H01L43/12

    CPC classification number: H01L43/10 ,  G01R33/098 ,  H01L43/12 ,  Y10T29/49117

    Abstract: A sensor and fabrication process are provided for forming reference layers with substantially orthogonal magnetization directions having zero offset with a small compensation angle. An exemplary embodiment includes a sensor layer stack of a magnetoresistive thin-film based magnetic field sensor, the sensor layer stack comprising a pinning layer; a pinned layer including a layer of amorphous material over the pinning layer, and a first layer of crystalline material over the layer of amorphous material; a nonmagnetic coupling layer over the pinned layer; a fixed layer over the nonmagnetic coupling layer; a tunnel barrier over the fixed layer; and a sense layer over the nonmagnetic intermediate layer. Another embodiment includes a sensor layer stack where a pinned layer including two crystalline layers separated by a amorphous layer.

    Magnetoresistive memory element and method of fabricating same
    47.
    发明授权
    Magnetoresistive memory element and method of fabricating same 有权
    磁阻存储元件及其制造方法

    公开(公告)号：US09553258B2

    公开(公告)日：2017-01-24

    申请号：US14860657

    申请日：2015-09-21

    Applicant: Everspin Technologies, Inc.

    Inventor： Renu Whig ,  Jijun Sun ,  Nicholas Rizzo ,  Jon Slaughter ,  Dimitri Houssameddine ,  Frederick Mancoff

    IPC: H01L21/8234 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L43/02 ,  G11C11/16

    CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

    Abstract: A magnetoresistive memory element (for example, a spin-torque magnetoresistive memory element), includes first and second dielectric layers, wherein at least one of the dielectric layers is a magnetic tunnel junction. The memory element also includes a free magnetic layer having a first surface in contact with the first dielectric layer and a second surface in contact with the second dielectric layer. The free magnetic layer, which is disposed between the first and second dielectric layers, includes (i) a first high-iron interface region located along the first surface of the free magnetic layer, wherein the first high-iron interface region has at least 50% iron by atomic composition, and (ii) a first layer of ferromagnetic material adjacent to the first high-iron interface region, the first high-iron interface region between the first layer of ferromagnetic material and the first surface of the free magnetic layer.

    Abstract translation: 磁阻存储元件（例如，自旋扭矩磁阻存储元件）包括第一和第二电介质层，其中至少一个电介质层是磁性隧道结。 存储元件还包括具有与第一介电层接触的第一表面和与第二介电层接触的第二表面的自由磁性层。 设置在第一和第二电介质层之间的自由磁性层包括（i）沿着自由磁性层的第一表面设置的第一高铁界面区域，其中第一高铁界面区域具有至少50 以及（ii）与第一高铁界面区域相邻的第一铁磁材料层，第一铁磁材料层与自由磁性层的第一表面之间的第一高铁界面区域。

    Magnetoresistive Structure having a Metal Oxide Tunnel Barrier and Method of Manufacturing Same
    49.
    发明申请
    Magnetoresistive Structure having a Metal Oxide Tunnel Barrier and Method of Manufacturing Same 审中-公开
    具有金属氧化物隧道屏障的磁阻结构及其制造方法

    公开(公告)号：US20150236253A1

    公开(公告)日：2015-08-20

    申请号：US14701831

    申请日：2015-05-01

    Applicant: Everspin Technologies, Inc.

    Inventor： Renu Whig ,  Jason Janesky ,  Nicholas Rizzo ,  Jon Slaughter ,  Dimitri Houssameddine

    IPC: H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01L43/02

    CPC classification number: H01L43/02 ,  B82Y10/00 ,  H01L27/222 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  Y10S977/935

    Abstract: In one aspect, the present inventions are directed to a magnetoresistive structure having a tunnel junction, and a process for manufacturing such a structure. The tunnel barrier may be formed between a free layer and a fixed layer in a plurality of repeating process of depositing a metal material and oxidizing at least a portion of the metal material. Where the tunnel barrier is formed by deposition of at least three metal materials interceded by an associated oxidization thereof, the oxidation dose associated with the second metal material may be greater than the oxidation doses associated with the first and third metal materials. In certain embodiments, the fixed layer may include a discontinuous layer of a metal, for example, Ta, in the fixed layer between two layers of a ferromagnetic material.

    Abstract translation: 一方面，本发明涉及具有隧道结的磁阻结构，以及制造这种结构的方法。 可以在沉积金属材料和氧化至少一部分金属材料的多个重复工艺中，在自由层和固定层之间形成隧道势垒。 在通过沉积由其相关氧化作用介入的至少三种金属材料形成隧道势垒的地方，与第二金属材料相关的氧化剂量可能大于与第一和第三金属材料相关联的氧化剂量。 在某些实施例中，固定层可以在两层铁磁材料之间的固定层中包括不连续的金属层，例如Ta。

    MRAM SYNTHETIC ANITFEROMAGNET STRUCTURE
    50.
    发明申请
    MRAM SYNTHETIC ANITFEROMAGNET STRUCTURE 有权
    MRAM合成ANITFEROMAGNET结构

    公开(公告)号：US20150021606A1

    公开(公告)日：2015-01-22

    申请号：US14303200

    申请日：2014-06-12

    Applicant: Everspin Technologies, Inc.

    Inventor： Srinivas V. Pietambaram ,  Bengt J. Akerman ,  Renu Whig ,  Jason Janesky ,  Nicholas D. Rizzo ,  Jon Slaughter

    IPC: H01L43/10 ,  H01L43/02

    CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L27/222 ,  H01L43/02 ,  H01L43/10

    Abstract: An MRAM bit (10) includes a free magnetic region (15), a fixed magnetic region (17) comprising an antiferromagnetic material, and a tunneling barrier (16) comprising a dielectric layer positioned between the free magnetic region (15) and the fixed magnetic region (17). The MRAM bit (10) avoids a pinning layer by comprising a fixed magnetic region exhibiting a well-defined high Hflop using a combination of high Hk (uniaxial anisotropy), high Hsat (saturation field), and ideal soft magnetic properties exhibiting well-defined easy and hard axes.

    Abstract translation: MRAM位（10）包括自由磁区（15），包括反铁磁材料的固定磁区（17）和隧道势垒（16），其包括位于自由磁区（15）和固定 磁区（17）。 MRAM位（10）通过使用高Hk（单轴各向异性），高Hsat（饱和磁场）和显示明确定义的理想软磁性质的组合，包括表现出明确的高Hflop的固定磁区，避免了钉扎层 容易和坚硬的轴。

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