公开(公告)号：US20060058670A1

公开(公告)日：2006-03-16

申请号：US10915177

申请日：2004-08-10

Applicant: Feng Lin ,  Qian Adams

Inventor： Feng Lin ,  Qian Adams

IPC: A61B8/06 ,  A61B8/12

CPC classification number: G03B42/06 ,  G01S7/52047 ,  G01S15/8915 ,  G01S15/8995

Abstract: A method and apparatus for ultrasound spatial compounding imaging with adjustable aperture controls is disclosed. The method and apparatus can improve the image quality of all frames by applying different aperture controls on each frame of the spatially compounded image. One or both of transmit and receive aperture controls may include preventing some element of the transducer array from transmitting or receiving, calculating weighting apodizations to combine with standard apodizations for each frame, or determining an aperture size based on an f-number for the transducer array for each frame.

Abstract translation: 公开了一种用于具有可调孔径控制的超声空间复合成像的方法和装置。 该方法和装置可以通过在空间复合图像的每个帧上应用不同的光圈控制来提高所有帧的图像质量。 发射和接收孔径控制中的一个或两个可以包括防止换能器阵列的一些元件发射或接收，计算加权变迹以与每个帧的标准变迹组合，或者基于换能器阵列的f数来确定孔径尺寸 对于每一帧。

公开(公告)号：US07009407B2

公开(公告)日：2006-03-07

申请号：US10782577

申请日：2004-02-19

Applicant: Feng Lin

Inventor： Feng Lin

IPC: G01R35/00

CPC classification number: G01R31/31727 ,  G01R31/3016

Abstract: A delay lock circuit includes a measuring path, a forward path, and a feedback path. The measuring path samples a pulse with a reference signal in a measurement to obtain a measured delay. The forward path delays the reference signal based on the measured delay to generate an internal signal. The feedback path includes a calibrating unit for generating the pulse based on a plurality of feedback signals generated from the reference signal. The delay lock circuit further includes a monitoring unit for monitoring the measurement. Based on the monitoring, the monitoring unit enables the calibrating unit to conditionally adjust the width of the pulse.

Abstract translation: 延迟锁定电路包括测量路径，前向路径和反馈路径。 测量路径在测量中用参考信号采样脉冲以获得测量的延迟。 正向路径基于所测量的延迟延迟参考信号以产生内部信号。 反馈路径包括用于基于从参考信号产生的多个反馈信号产生脉冲的校准单元。 延迟锁定电路还包括用于监视测量的监视单元。 基于监控，监控单元使校准单元有条件地调整脉冲的宽度。

公开(公告)号：US20060044891A1

公开(公告)日：2006-03-02

申请号：US10931472

申请日：2004-08-31

Applicant: Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

Inventor： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

IPC: G11C7/00

CPC classification number: G11C7/109 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222

Abstract: A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

公开(公告)号：US06930955B2

公开(公告)日：2005-08-16

申请号：US10851081

申请日：2004-05-24

Applicant: Brian Johnson ,  Brent Keeth ,  Feng Lin

Inventor： Brian Johnson ,  Brent Keeth ,  Feng Lin

IPC: G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/4076

CPC classification number: G11C7/222 ,  G11C7/1072 ,  G11C11/4076

Abstract: A method and apparatus for managing the variable timing of internal clock signals derived from an external clock signal in order to compensate for uncertainty and variations in the amount of read clock back timing relative to data flow to achieve a specified read latency. A reset signal is generated at DRAM initialization and starts an first counter, which counts external clock cycles, and is also passed through the slave delay line of the delay lock loop to start a second counter. The counters run continuously once started and the difference in count values represent the internal delay as an external clock signal passes through the delay lock loop to produce an internal read clock signal. An internal read latency value is used to offset either counter to account for the internal read latency of the DRAM circuit. Once the non-offset counter is equivalent to the offset counter, read data is placed on an output line with a specified read latency and synchronized with the external read clock.

Abstract translation: 一种用于管理从外部时钟信号导出的内部时钟信号的可变定时的方法和装置，以便补偿相对于数据流的读取时钟反馈时序的不确定性和变化，以实现指定的读取等待时间。 在DRAM初始化时产生复位信号，并启动计数外部时钟周期的第一计数器，并且还通过延迟锁定循环的从延迟线来启动第二个计数器。 一旦启动，计数器连续运行，当外部时钟信号通过延迟锁定环路以产生内部读取时钟信号时，计数值的差异代表内部延迟。 内部读延迟值用于抵消DRAM电路的内部读延迟。 一旦非偏移计数器等效于偏移计数器，读取数据将放置在具有指定读延迟并与外部读时钟同步的输出线上。

公开(公告)号：US20050116751A1

公开(公告)日：2005-06-02

申请号：US11028090

申请日：2005-01-03

Applicant: Feng Lin ,  J. Johnson

Inventor： Feng Lin ,  J. Johnson

IPC: G11C7/22 ,  G11C29/02 ,  H03L7/06

CPC classification number: G11C29/12015 ,  G11C7/02 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012

Abstract: Delay-locked loops, signal locking methods and devices and system incorporating delay-locked loops are described. A delay-locked loop includes a forward delay path, a feedback delay path, a phase detector and a timer circuit. The forward delay path alternatively couples to an external clock signal and to an internal test signal. The phase detector adjusts a delay line based upon the phase differences of a feedback signal and the external clock signal. The timer circuit switches the test signal into the forward delay path and measures the time of traversal of the test signal around the forward delay path and the feedback delay path and generates a time constant for configuring the phase detector's update period. The phase detector is thereafter able to stabilize at an improved rate.

公开(公告)号：US20050101865A1

公开(公告)日：2005-05-12

申请号：US10703903

申请日：2003-11-07

Applicant: Xiaohui Hao ,  Feng Lin ,  Richard Chiao

Inventor： Xiaohui Hao ,  Feng Lin ,  Richard Chiao

IPC: G01S7/52 ,  G01S15/89 ,  A61B8/00

CPC classification number: G01S7/52038 ,  G01S7/52047 ,  G01S15/8995

Abstract: Certain embodiments include a system and method for improved compound imaging using a plurality of imaging modes. In an embodiment, a plurality of echo signals are received in response to a plurality of beams formed based on different imaging modes corresponding to different steering angles, such as steered or non-steered angles. The plurality of echo signals is compounded to form a compound image. In an embodiment, the imaging mode includes at least one of harmonic, fundamental, coded harmonic, and variable frequency imaging. Parameters may be generated for the plurality of beams formed based on different imaging modes corresponding to different steering angles. Additionally, the parameters may be stored. The echo signals may be filtered. Imaging mode may be controlled based on steering angle. Employing different imaging modes based on steering angles for spatial compound imaging helps reduce grating lobe artifacts while improving speckle reduction effect.

Abstract translation: 某些实施例包括用于使用多个成像模式改进复合成像的系统和方法。 在一个实施例中，响应于基于对应于不同转向角的不同成像模式形成的多个波束（例如转向或非转向角）来接收多个回波信号。 多个回波信号被复合以形成复合图像。 在一个实施例中，成像模式包括谐波，基波，编码谐波和可变频率成像中的至少一个。 可以针对对应于不同转向角的不同成像模式形成的多个波束产生参数。 另外，可以存储参数。 可以对回波信号进行滤波。 成像模式可以基于转向角来控制。 基于空间复合成像的转向角采用不同的成像模式有助于减少光栅叶片伪影，同时提高散斑效果。

公开(公告)号：US20050083099A1

公开(公告)日：2005-04-21

申请号：US11003144

申请日：2004-12-03

Applicant: Feng Lin

Inventor： Feng Lin

IPC: G11C7/10 ,  G11C7/22 ,  H03L7/07 ,  H03L7/081 ,  H04L7/02 ,  H03K3/00

CPC classification number: G11C7/1087 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222 ,  H03L7/07 ,  H03L7/0812 ,  H04L7/02

Abstract: A clock generator comprises a master delay locked loop (DLL) and a slave DLL to capture a data signal. The slave DLL generates a slave output signal based on a clock signal. The master DLL receives the slave output signal and compensates variations in delays of the data and clock signals to generate a capture clock signal. When the master and slave DLLs are locked, the capture clock signal is center aligned with the data signal.

Abstract translation: 时钟发生器包括主延迟锁定环（DLL）和从属DLL以捕获数据信号。 从机DLL根据时钟信号产生从机输出信号。 主DLL接收从机输出信号并补偿数据和时钟信号延迟的变化，以产生捕获时钟信号。 当主和从DLL被锁定时，捕获时钟信号与数据信号中心对准。

公开(公告)号：US06868504B1

公开(公告)日：2005-03-15

申请号：US09652632

申请日：2000-08-31

Applicant: Feng Lin

Inventor： Feng Lin

IPC: G11C11/407 ,  G06F1/10 ,  G06F1/12 ,  G11C8/02 ,  G11C11/409 ,  H03K5/14 ,  H03L7/00 ,  H03L7/06 ,  H03L7/081 ,  H03L7/087 ,  H03L7/099 ,  G06F1/04

CPC classification number: G06F1/10 ,  G11C7/1072 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/087 ,  H03L7/0998 ,  Y10T307/951

Abstract: An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and voltage (PVT) variations while a second portion, in series with the first portion, provides a variable amount of delay that substantially tracks changes in process, temperature, and voltage variations. By combining, or interleaving, the two types of delay, single and dual locked loops constructed using the present invention achieve a desired jitter performance under PVT variations, dynamically track the delay variations of one coarse tap without a large number of delay taps, and provide for quick and tight locking. Methods of operating delay lines and locked loops are also disclosed.

公开(公告)号：US06845458B2

公开(公告)日：2005-01-18

申请号：US10731679

申请日：2003-12-09

Applicant: Feng Lin

Inventor： Feng Lin

IPC: G11C11/407 ,  G06F1/10 ,  G06F1/12 ,  G11C8/02 ,  G11C11/409 ,  H03K5/14 ,  H03L7/00 ,  H03L7/06 ,  H03L7/081 ,  H03L7/087 ,  H03L7/099

CPC classification number: G06F1/10 ,  G11C7/1072 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/087 ,  H03L7/0998 ,  Y10T307/951

Abstract: An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and voltage (PVT) variations while a second portion, in series with the first portion, provides a variable amount of delay that substantially tracks changes in process, temperature, and voltage variations. By combining, or interleaving, the two types of delay, single and dual locked loops constructed using the present invention achieve a desired jitter performance under PVT variations, dynamically track the delay variations of one coarse tap without a large number of delay taps, and provide for quick and tight locking. Methods of operating delay lines and locked loops are also disclosed.

Abstract translation: 用于锁相和延迟锁定环的交错延迟线包括第一部分，其基本上独立于过程，温度和电压（PVT）变化提供可变量的延迟，而与第一部分串联的第二部分提供 可变量的延迟，其基本上跟踪过程，温度和电压变化的变化。 通过组合或交织两种类型的延迟，使用本发明构造的单锁定环和双锁定环在PVT变化下实现期望的抖动性能，动态地跟踪一个粗抽头的延迟变化而没有大量延迟抽头，并提供 用于快速和紧密的锁定。 还公开了延迟线和锁定环路的操作方法。

公开(公告)号：US06839301B2

公开(公告)日：2005-01-04

申请号：US10425069

申请日：2003-04-28

Applicant: Feng Lin ,  J. Brian Johnson

Inventor： Feng Lin ,  J. Brian Johnson

IPC: G11C7/22 ,  G11C29/02 ,  G11C8/00

CPC classification number: G11C29/12015 ,  G11C7/02 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012

Abstract: Delay-locked loops, signal locking methods and devices and system incorporating delay-locked loops are described. A delay-locked loop includes a forward delay path, a feedback delay path, a phase detector and a timer circuit. The forward delay path alternatively couples to an external clock signal and to an internal test signal. The phase detector adjusts a delay line based upon the phase differences of a feedback signal and the external clock signal. The timer circuit switches the test signal into the forward delay path and measures the time of traversal of the test signal around the forward delay path and the feedback delay path and generates a time constant for configuring the phase detector's update period. The phase detector is thereafter able to stabilize at an improved rate.

Abstract translation: 描述了延迟锁定环路，信号锁定方法和装置以及包含延迟锁定环路的系统。 延迟锁定环包括正向延迟路径，反馈延迟路径，相位检测器和定时器电路。 前向延迟路径交替耦合到外部时钟信号和内部测试信号。 相位检测器根据反馈信号和外部时钟信号的相位差调整延迟线。 定时器电路将测试信号切换到正向延迟路径，并测量在前向延迟路径和反馈延迟路径周围的测试信号遍历时间，并产生用于配置相位检测器更新周期的时间常数。 此后，相位检测器能够以更高的速率稳定。