公开(公告)号：US09437588B1

公开(公告)日：2016-09-06

申请号：US14742935

申请日：2015-06-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jia Zeng ,  Jongwook Kye ,  Harry J. Levinson

IPC: H01L29/66 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L27/088

CPC classification number: H01L27/0207 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286 ,  H01L2027/11875

Abstract: A dense library architecture using an M0 hand-shake and the method of forming the layout are disclosed. Embodiments include forming first and second active areas on a substrate, at the top and bottom of a cell, separated from each other; forming first through third gate lines perpendicular to the active areas, where the first and third gate lines are dummy gates at the cell edges; forming trench silicide segments on each of the active areas, between the first, second, and third gate lines; forming first and second M1 metal lines between the first and second gate lines and the second and third gate lines, respectively; forming a M0 segment between the first and second active regions perpendicular to the M1 metal lines; forming a CB between the M0 segment and the second gate line; and forming a V0 from the first metal line to the M0 segment.

Abstract translation: 公开了使用M0手摇的密集库结构和形成布局的方法。 实施例包括在基板上，在电池的顶部和底部形成彼此分离的第一和第二有源区; 形成垂直于有源区的第一至​​第三栅极线，其中第一和第三栅极线在单元边缘处是伪栅极; 在所述第一，第二和第三栅极线之间的所述有源区域中的每一个上形成沟槽硅化物段; 在第一和第二栅极线与第二和第三栅极线之间分别形成第一和第二M1金属线; 在垂直于M1金属线的第一和第二有源区之间形成M0段; 在M0段和第二栅极线之间形成CB; 并从第一金属线形成V0至M0段。

公开(公告)号：US20150331988A1

公开(公告)日：2015-11-19

申请号：US14809698

申请日：2015-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Yuan ,  Juhan Kim ,  Jongwook Kye ,  Mahbub Rashed

IPC: G06F17/50 ,  H01L23/522

CPC classification number: G06F17/5077 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments described herein provide approaches for improved circuit routing using a wide-edge pin. Specifically, provided is an integrated circuit (IC) device comprising a standard cell having a first metal layer (M1) pin coupled to a second metal layer (M2) wire at a via. The M1 pin has a width greater than a width of the via sufficient to satisfy an enclosure rule for the via, while the M1 pin extends vertically past the via a distance substantially equal to or greater than zero. This layout increases the number of available pin access points within the standard cell and thus improves routing efficiency and chip size.

Abstract translation: 本文描述的实施例提供了使用宽边缘引脚改进电路布线的方法。 具体地，提供了一种集成电路（IC）装置，其包括具有在通孔处耦合到第二金属层（M2）线的第一金属层（M1）引脚的标准单元。 M1引脚的宽度大于通孔的宽度，足以满足通孔的外壳规则，而M1引脚垂直延伸超过基本上等于或大于零的距离。 该布局增加了标准单元内可用引脚接入点的数量，从而提高了布线效率和芯片尺寸。

公开(公告)号：US09159724B2

公开(公告)日：2015-10-13

申请号：US14161063

申请日：2014-01-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yan Wang ,  Yuansheng Ma ,  Jongwook Kye ,  Mahbub Rashed

IPC: H01L29/40 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/088 ,  H01L21/76895 ,  H01L21/823475 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/092

Abstract: An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a gate cut region across the first gate structure, the second gate structure, or a combination thereof; providing a first gate contact over the first gate structure; providing a second gate contact over the second gate structure; and providing a diffusion contact structure coupling the first gate contact to the second gate contact, the diffusion contact structure having vertices within the gate cut region.

Abstract translation: 公开了一种使用扩散接触结构提供基于交叉耦合的设计的方法。 实施例包括在衬底上提供第一和第二栅极结构; 提供横跨所述第一栅极结构，所述第二栅极结构或其组合的栅极截止区域; 在第一栅极结构上提供第一栅极接触; 在所述第二栅极结构上提供第二栅极接触; 以及提供将所述第一栅极接触耦合到所述第二栅极接触的扩散接触结构，所述扩散接触结构在所述栅极切割区域内具有顶点。

公开(公告)号：US09122830B2

公开(公告)日：2015-09-01

申请号：US13908096

申请日：2013-06-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Juhan Kim ,  Jongwook Kye ,  Mahbub Rashed

IPC: H01L27/02 ,  G06F17/50 ,  H01L27/118 ,  H01L23/522

CPC classification number: G06F17/5077 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments described herein provide approaches for improved circuit routing using a wide-edge pin. Specifically, provided is an integrated circuit (IC) device comprising a standard cell having a first metal layer (M1) pin coupled to a second metal layer (M2) wire at a via. The M1 pin has a width greater than a width of the via sufficient to satisfy an enclosure rule for the via, while the M1 pin extends vertically past the via a distance substantially equal to or greater than zero. This layout increases the number of available pin access points within the standard cell and thus improves routing efficiency and chip size.

Abstract translation: 本文描述的实施例提供了使用宽边缘引脚改进电路布线的方法。 具体地，提供了一种集成电路（IC）装置，其包括具有在通孔处耦合到第二金属层（M2）线的第一金属层（M1）引脚的标准单元。 M1引脚的宽度大于通孔的宽度，足以满足通孔的外壳规则，而M1引脚垂直延伸超过基本上等于或大于零的距离。 该布局增加了标准单元内可用引脚接入点的数量，从而提高了布线效率和芯片尺寸。

公开(公告)号：US20150243515A1

公开(公告)日：2015-08-27

申请号：US14186396

申请日：2014-02-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Jongwook Kye ,  Harry J. Levinson

IPC: H01L21/308 ,  H01L21/768 ,  H01L21/306 ,  G06F17/50

CPC classification number: H01L21/3088 ,  G03F1/70 ,  G03F7/0002 ,  G06F17/5068 ,  H01L21/0274 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/76877

Abstract: A method involving identifying a pattern for an overall target cut mask to be used in patterning line-type features that includes a target non-rectangular opening feature having an inner, concave corner, decomposing the overall target cut mask pattern into first and second sub-target patterns, wherein the first sub-target pattern comprises a first rectangular-shaped opening feature corresponding to a first portion, but not all, of the target non-rectangular opening feature and the second sub-target pattern comprises a second rectangular-shaped opening feature corresponding to a second portion, but not all, of the target non-rectangular opening feature, the first and second openings overlapping adjacent the inner, concave corner, and generating first and second sets of mask data corresponding to the first and second sub-target patterns, wherein at least one of the first and second sets of mask data is generated based upon an identified contact-to-end-of-cut-line spacing rule.

Abstract translation: 一种涉及识别用于构图线型特征的整体目标切割掩模的图案的方法，所述线型特征包括具有内凹角的目标非矩形开口特征，将总体目标切割掩模图案分解为第一和第二子图， 目标图案，其中所述第一子目标图案包括与所述目标非矩形开口特征和所述第二子目标图案的第一部分但不是全部相对应的第一矩形开口特征，所述第一子目标图案包括第二矩形开口特征， 特征对应于目标非矩形开口特征的第二部分但不是全部，第一和第二开口与内凹角相邻重叠，并且生成对应于第一和第二子图的第一和第二组掩模数据， 目标图案，其中基于所识别的切割线间距规则，生成第一组和第二组掩模数据中的至少一个。

公开(公告)号：US09105510B2

公开(公告)日：2015-08-11

申请号：US14461745

申请日：2014-08-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Youngtag Woo ,  Jongwook Kye ,  Dinesh Somasekhar

IPC: H01L21/8234 ,  H01L27/11 ,  H01L21/308 ,  H01L27/088 ,  H01L21/8238

CPC classification number: H01L27/1108 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/11

Abstract: Methodology enabling a generation of fins having a variable fin pitch less than 40 nm, and the resulting device are disclosed. Embodiments include: forming a hardmask on a substrate; providing first and second mandrels on the hardmask; providing a first spacer on each side of each of the first and second mandrels; removing the first and second mandrels; providing, after removal of the first and second mandrels, a second spacer on each side of each of the first spacers; and removing the first spacers.

Abstract translation: 公开了能够产生具有可变翅片间距小于40nm的翅片的方法，并且所得到的装置被公开。 实施例包括：在基板上形成硬掩模; 在硬掩模上提供第一和第二心轴; 在每个第一和第二心轴的每一侧上提供第一间隔件; 去除第一和第二心轴; 在移除所述第一和第二心轴之后，在每个所述第一间隔件的每一侧上提供第二间隔件; 并移除第一间隔物。

公开(公告)号：US08966412B1

公开(公告)日：2015-02-24

申请号：US14035329

申请日：2013-09-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Jongwook Kye ,  Harry J. Levinson

IPC: G06F17/50

CPC classification number: G03F1/70 ,  G03F7/70283 ,  G03F7/70466

Abstract: One method disclosed herein involves, among other things, identifying a plurality of features within an overall pattern layout that cannot be decomposed using the SADP process, wherein at least first and second adjacent features are required to be same-color features, decreasing a spacing between the first and second adjacent features such that the first feature and the second feature become different-color features so as to thereby render the plurality of features decomposable using the SADP process, decomposing the overall pattern layout into a mandrel mask pattern and a block mask pattern, and generating mask data sets corresponding to the mandrel mask pattern and the block mask pattern.

Abstract translation: 本文公开的一种方法除其他外包括识别不能使用SADP过程分解的整体图案布局中的多个特征，其中至少第一和第二相邻特征需要是相同颜色的特征， 所述第一和第二相邻特征使得所述第一特征和所述第二特征变为不同颜色特征，从而使得所述多个特征可以使用所述SADP处理分解，将所述整体图案布局分解为心轴掩模图案和块掩模图案 并且生成与心轴掩模图案和块掩模图案相对应的掩模数据集。

公开(公告)号：US08962483B2

公开(公告)日：2015-02-24

申请号：US13799539

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Youngtag Woo ,  Dinesh Somasekhar ,  Juhan Kim ,  Yunfei Deng ,  Jongwook Kye

IPC: H01L21/3065 ,  H01L21/308 ,  G03F7/26

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L27/0207 ,  H01L27/11

Abstract: Methodology enabling a generation of an interconnection design utilizing an SIT process is disclosed. Embodiments include: providing a hardmask on a substrate; forming a mandrel layer on the hardmask including: first and second vertical portions extending along a vertical direction and separated by a horizontal distance; and a plurality of horizontal portions extending in a horizontal direction, wherein each of the horizontal portions is positioned between the first and second vertical portions and at a different position along the vertical direction; and forming a spacer layer on outer edges of the mandrel layer.

Abstract translation: 公开了能够利用SIT过程产生互连设计的方法。 实施例包括：在基板上提供硬掩模; 在所述硬掩模上形成心轴层，包括：沿着垂直方向延伸并分开水平距离的第一和第二垂直部分; 以及沿水平方向延伸的多个水平部分，其中每个水平部分位于第一和第二垂直部分之间以及沿着垂直方向的不同位置; 以及在心轴层的外边缘上形成间隔层。

公开(公告)号：US08918746B1

公开(公告)日：2014-12-23

申请号：US14018074

申请日：2013-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Jongwook Kye ,  Harry J. Levinson

IPC: G06F17/50 ,  G06F19/00 ,  G21K5/00 ,  G01N23/00 ,  G03F1/00 ,  H01L21/00

CPC classification number: H01L27/0207

Abstract: Methodologies and an apparatus enabling a selection of design rules to improve a density of features of an IC design are disclosed. Embodiments include: determining a feature overlapping a grating pattern of an IC design, the grating pattern including a plurality of grating structures; determining a shape of a cut pattern overlapping the grating pattern; and selecting one of a plurality of rules for the feature based on the determined shape.

Abstract translation: 公开了能够选择设计规则以提高IC设计的特征密度的方法和装置。 实施例包括：确定与IC设计的光栅图案重叠的特征，所述光栅图案包括多个光栅结构; 确定与所述光栅图案重叠的切割图案的形状; 以及基于所确定的形状来选择所述特征的多个规则中的一个。

公开(公告)号：US08916441B2

公开(公告)日：2014-12-23

申请号：US13893684

申请日：2013-05-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mahbub Rashed ,  Juhan Kim ,  Yunfei Deng ,  Jongwook Kye ,  Suresh Venkatesan

IPC: H01L21/8234 ,  H01L21/8244 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/6681

Abstract: Embodiments of the present invention provide a novel method and structure for forming finFET structures that comprise standard cells. An H-shaped cut mask is used to reduce the number of fins that need to be removed, hence increasing the fin efficiency.

Abstract translation: 本发明的实施例提供了用于形成包含标准单元的finFET结构的新颖方法和结构。 使用H形切割掩模来减少需要去除的翅片的数量，从而提高翅片效率。