公开(公告)号：US20210273160A1

公开(公告)日：2021-09-02

申请号：US16802562

申请日：2020-02-27

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Desmond Jia Jun LOY ,  Eng Huat TOH ,  Shyue Seng TAN

IPC: H01L45/00 ,  H01L27/24

Abstract: A memory device may be provided including one or more bottom electrodes, one or more mask elements, one or more top electrodes and a switching layer. The bottom electrode(s) may include a first bottom electrode, the mask element(s) may include a first mask element and the top electrode(s) may include a first top electrode. The first mask element may be arranged over a first part of the first bottom electrode. The first top electrode may be arranged over and in contact with the first mask element. The switching layer may be arranged to extend over a second part of the first bottom electrode, and along a first side surface of the first mask element and further along a first side surface of the first top electrode. The first side surfaces of the first mask element and the first top electrode may face a same direction.

公开(公告)号：US20210225936A1

公开(公告)日：2021-07-22

申请号：US16744223

申请日：2020-01-16

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Lanxiang WANG ,  Shyue Seng TAN ,  Eng Huat TOH ,  Benfu LIN

IPC: H01L27/24 ,  H01L45/00

Abstract: A memory device may be provided, including a substrate; one or more bottom electrodes arranged over the substrate; one or more switching layers arranged over the one or more bottom electrodes; and a plurality of top electrodes arranged over the one or more switching layers. Each of the one or more bottom electrodes may include at least one corner tip facing the switching layer, and an angle of each of the at least one corner tip may be less than ninety degrees.

公开(公告)号：US20210135101A1

公开(公告)日：2021-05-06

申请号：US16672632

申请日：2019-11-04

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Desmond Jia Jun LOY ,  Eng Huat TOH ,  Shyue Seng TAN ,  Steven SOSS

IPC: H01L45/00

Abstract: A memory device may include at least one inert electrode, at least one active electrode, an insulating element arranged at least partially between the at least one active electrode and the at least one inert electrode, and a switching element arranged under the insulating element. The switching element may be arranged at least partially between the at least one active electrode and the at least one inert electrode. The switching element may include a first end and a second end contacting the at least one active electrode; and a middle segment between the first end and the second end, where the middle segment may at least partially contact the at least one inert electrode.

公开(公告)号：US20210010997A1

公开(公告)日：2021-01-14

申请号：US16505733

申请日：2019-07-09

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Xinshu CAI ,  Shyue Seng TAN ,  Eng Huat TOH ,  Kiok Boone Elgin QUEK

IPC: G01N33/487 ,  G01N27/447

Abstract: In a non-limiting embodiment, a device may include a substrate having conducting lines thereon. One or more fin structures may be arranged over the substrate. Each fin structure may include a sensor arranged over the substrate and around the fin structure. The sensor may include a self-aligned first sensing electrode and a self-aligned second sensing electrode arranged around the fin structure. The first sensing electrode and the second sensing electrode each may include a first portion lining a sidewall of the fin structure and a second portion arranged laterally from the first portion. At least the first portion of the first sensing electrode and the first portion of the second sensing electrode may define a sensing cavity of the sensor. The second portion of the first sensing electrode and the second portion of the second sensing electrode may be electrically coupled to the conducting lines.

公开(公告)号：US20200292631A1

公开(公告)日：2020-09-17

申请号：US16297880

申请日：2019-03-11

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Yongshun SUN ,  Eng Huat TOH ,  Kiok Boone Elgin QUEK

IPC: G01R33/00 ,  H01L43/14 ,  H01L43/06 ,  H01L27/22 ,  G01R33/07

Abstract: A device having a Hall effect sensor is provided. The Hall effect sensor includes a sensor well and a Hall plate disposed within the sensor well. The Hall plate includes a first current terminal and a second current terminal configured to flow a current through the Hall plate, and the Hall plate further includes a first sensing terminal and a second sensing terminal configured to sense a Hall voltage. A separation layer and a separation well are disposed within the sensor well, as well as surround the Hall plate and isolate the Hall plate. At least one of a current sensitivity and a resistance of the Hall effect sensor is tunable based on an adjustable thickness of the Hall plate. The thickness of the Hall plate is adjustable based at least in part on implants in the separation layer and/or a bias voltage applied to the separation layer.

公开(公告)号：US20190148454A1

公开(公告)日：2019-05-16

申请号：US16223074

申请日：2018-12-17

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Xuan Anh TRAN ,  Eng Huat TOH ,  Shyue Seng TAN ,  Yuan SUN ,  Elgin Kiok Boone QUEK

IPC: H01L27/24 ,  H01L27/22 ,  H01L45/00

CPC classification number: H01L27/2463 ,  H01L27/226 ,  H01L27/2445 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1675

Abstract: Memory devices and manufacturing methods thereof are presented. A memory device a substrate and a memory cell having at least one selector and a storage element. The selector includes a well of a first polarity type disposed in the substrate, a region of a second polarity type disposed over the well and in the substrate, and first and second regions of the first polarity type disposed adjacent to the region of the second polarity type. The storage element includes a programmable resistive layer disposed on the region of the second polarity type and an electrode disposed over the programmable resistive layer.

公开(公告)号：US20190139607A1

公开(公告)日：2019-05-09

申请号：US15807160

申请日：2017-11-08

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Shyue Seng TAN ,  Danny Pak-Chum SHUM ,  Eng Huat TOH

IPC: G11C16/04 ,  H01L29/788 ,  H01L29/66 ,  G11C16/10 ,  H01L27/11517

CPC classification number: G11C16/0433 ,  G11C16/045 ,  G11C16/10 ,  G11C17/04 ,  G11C2216/10 ,  G11C2216/26 ,  H01L27/11517 ,  H01L29/66825 ,  H01L29/7885

Abstract: A method of forming a FG OTP/MTP cell with a P+ drain junction at the NCAP region and the resulting device are provided. Embodiments include forming MVPW regions laterally separated in a p-sub; forming a MVNW region in the p-sub between the MVPW regions; forming a first RX, a second RX, and a third RX in the MVPW and MVNW regions, respectively; forming a first and a second pair of floating gates separated over and perpendicular to the first and second RX and the second and third RX, respectively; forming a N+ source region between and adjacent to each FG of the first and the second pair in the second RX; and forming a pair of P+ drain regions in the second RX, each P+ drain region adjacent to a FG of the first pair and a FG of the second pair and remote from the N+ source region.

公开(公告)号：US20190115350A1

公开(公告)日：2019-04-18

申请号：US16217064

申请日：2018-12-12

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Eng Huat TOH ,  Shyue Seng TAN ,  Elgin Kiok Boone QUEK ,  Danny Pak-Chum SHUM

IPC: H01L27/102 ,  G11C11/39 ,  H01L29/74 ,  H01L29/66

Abstract: Devices and methods for forming a device are presented. The device includes a substrate having a well of a first polarity type and a thyristor-based memory cell. The thyristor-based memory cell includes at least a first region of a second polarity type adjacent to the well, a gate which serves as a second word line disposed on the substrate, at least a first layer of the first polarity type disposed adjacent to the first region of the second polarity type and adjacent to the gate, and at least a heavily doped first layer of the second polarity type disposed on the first layer of the first polarity type and adjacent to the gate. At least the heavily doped first layer of the second polarity type is self-aligned with side of the gate.

公开(公告)号：US20190103474A1

公开(公告)日：2019-04-04

申请号：US15724230

申请日：2017-10-03

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Eng Huat TOH ,  Shyue Seng TAN ,  Kiok Boone Elgin QUEK

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78

Abstract: A method of sidewall engineering with negative capacitance materials is disclosed. For example, the negative capacitance material is a ferroelectric material. The method includes providing a dielectric liner on the sidewall of the gate and providing a negative capacitance liner or spacer over the dielectric liner. In one embodiment, the dielectric liner is an oxide liner and the negative capacitance liner or spacer is a ferroelectric liner or spacer. The engineered negative capacitance liner or spacer enhances the gate-to-S/D region and gate-to-contact coupling and hence the device ION-IOFF performance is improved.

公开(公告)号：US20190036011A1

公开(公告)日：2019-01-31

申请号：US15661826

申请日：2017-07-27

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Bin LIU ,  Eng Huat TOH ,  Ruchil Kumar JAIN

IPC: H01L43/04 ,  H01L43/06 ,  H01L43/14 ,  G01R33/07 ,  G01R33/02 ,  G01R33/00

CPC classification number: H01L43/04 ,  G01R33/0052 ,  G01R33/0206 ,  G01R33/077 ,  H01L27/22 ,  H01L43/065 ,  H01L43/14

Abstract: A method of forming a 3D Hall effect sensor and the resulting device are provided. Embodiments include forming a p-type well in a substrate; forming a first n-type well in a first region surrounded by the p-type well in top view; forming a second n-type well in a second region surrounding the p-type well; providing n-type dopant in the first and second n-type wells; and providing p-type dopant in the p-type well and the first n-type well.