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    LATERAL BIPOLAR JUNCTION TRANSISTOR AND METHOD
    42.
    发明申请
    LATERAL BIPOLAR JUNCTION TRANSISTOR AND METHOD 有权

    公开(公告)号：US20220376093A1

    公开(公告)日：2022-11-24

    申请号：US17324183

    申请日：2021-05-19

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Alexander M. Derrickson ,  Richard F. Taylor, III ,  Mankyu Yang ,  Alexander L. Martin ,  Judson R. Holt ,  Jagar Singh

    IPC: H01L29/735 ,  H01L21/84 ,  H01L29/739 ,  H01L29/66 ,  H01L27/12 ,  H01L29/10 ,  H01L29/08

    Abstract: Disclosed is a semiconductor structure including at least one bipolar junction transistor (BJT), which is uniquely configured so that fabrication of the BJT can be readily integrated with fabrication of complementary metal oxide semiconductor (CMOS) devices on an advanced silicon-on-insulator (SOI) wafer. The BJT has an emitter, a base, and a collector laid out horizontally across an insulator layer and physically separated. Extension regions extend laterally between the emitter and the base and between the base and the collector and are doped to provide junctions between the emitter and the base and between the base and the collector. Gate structures are on the extension regions. The emitter, base, and collector are contacted. Optionally, the gate structures and a substrate below the insulator layer are contacted and can be biased to optimize BJT performance. Optionally, the structure further includes one or more CMOS devices. Also disclosed is a method of forming the structure.

    Structure providing charge controlled electronic fuse
    43.
    发明授权
    Structure providing charge controlled electronic fuse 有权

    公开(公告)号：US11387353B2

    公开(公告)日：2022-07-12

    申请号：US16907600

    申请日：2020-06-22

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Jagar Singh ,  Sudarshan Narayanan ,  Alvin J. Joseph ,  William J. Taylor, Jr. ,  Jeffrey B. Johnson

    IPC: H01L29/68 ,  H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L27/112

    Abstract: A structure includes a first source/drain region and a second source/drain region in a semiconductor body; and a trench isolation between the first and second source/drain regions in the semiconductor body. A first doping region is about the first source/drain region, a second doping region about the second source/drain region, and the trench isolation is within the second doping region. A third doping region is adjacent to the first doping region and extend partially into the second doping region to create a charge trap section. A gate conductor of a gate structure is over the trench isolation and the first, second, and third doping regions. The charge trap section creates a charge controlled e-fuse operable by applying a stress voltage to the gate conductor.

    SEMICONDUCTOR DEVICE WITH DOPED REGION ADJACENT ISOLATION STRUCTURE IN EXTENSION REGION
    48.
    发明申请
    SEMICONDUCTOR DEVICE WITH DOPED REGION ADJACENT ISOLATION STRUCTURE IN EXTENSION REGION 有权

    公开(公告)号：US20210126126A1

    公开(公告)日：2021-04-29

    申请号：US16662276

    申请日：2019-10-24

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Jagar Singh ,  Luigi Pantisano ,  Anvitha Shampur ,  Frank Scott Johnson ,  Srikanth Balaji Samavedam

    IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

    Abstract: A semiconductor device is disclosed including a semiconductor layer, a first well doped with dopants of a first conductivity type defined in the semiconductor layer, a second well doped with dopants of a second conductivity type different than the first conductivity type defined in the semiconductor layer adjacent the first well to define a PN junction between the first and second wells, and an isolation structure positioned in the second well. The semiconductor device also includes a first source/drain region positioned in the first well, a second source/drain region positioned in the second well adjacent a first side of the isolation structure, a doped region positioned in the second well adjacent a second side of the isolation structure, and a gate structure positioned above the semiconductor layer, wherein the gate structure vertically overlaps a portion of the doped region.

    Lateral bipolar transistor
    50.
    发明授权
    Lateral bipolar transistor 有权

    公开(公告)号：US11967635B2

    公开(公告)日：2024-04-23

    申请号：US17533805

    申请日：2021-11-23

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Jagar Singh ,  Randy L. Wolf

    IPC: H01L29/735 ,  H01L29/06 ,  H01L29/161 ,  H01L29/66

    CPC classification number: H01L29/735 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/6625

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base region within a semiconductor substrate material; a shallow trench isolation structure extending into the semiconductor substrate material and bounding the extrinsic base region; an emitter region adjacent to the shallow trench isolation structure and on a side of the extrinsic base region; and a collector region adjacent to the shallow trench isolation structure and on an opposing side of the extrinsic base region.

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