公开(公告)号：US5614864A

公开(公告)日：1997-03-25

申请号：US536405

申请日：1995-09-29

Applicant: Frederic M. Stubbe ,  Daryush Shamlou ,  Kashif A. Ahmed ,  Guangming Yin

Inventor： Frederic M. Stubbe ,  Daryush Shamlou ,  Kashif A. Ahmed ,  Guangming Yin

IPC: H03F3/45

CPC classification number: H03F3/45475 ,  H03F3/45932 ,  H03F2203/45528

Abstract: A converter for converting a single-ended input V.sub.IN to a differential output signal V.sub.OUT through positive and negative output terminals is disclosed. The converter comprises a fully differential amplifier with one of its input terminals coupled to the single-ended input and its other input terminal coupled to a fixed voltage. The converter also has a first resistor ("R.sub.1 ") coupled between the single-ended input and the positive input terminal of the fully differential amplifier, a second resistor ("R.sub.2 ") coupled between the fixed voltage and the negative input terminal of the fully differential amplifier, a third resistor ("R.sub.3 ") coupled between the positive input terminal and the negative output terminal of the fully differential amplifier, and a fourth resistor ("R.sub.4 ") coupled between the negative input terminal and the positive output terminal, wherein the values of such resistors are governed by: ##EQU1## The same principles can be applied to differential-to-single-ended converters as well.

Abstract translation: 公开了一种通过正和负输出端将单端输入VIN转换为差分输出信号VOUT的转换器。 该转换器包括全差分放大器，其一个输入端耦合到单端输入端，其另一输入端耦合到一固定电压。 转换器还具有耦合在全差分放大器的单端输入端和正输入端之间的第一电阻（“R1”），耦合在固定电压和负输入端之间的第二电阻（“R2”） 全差分放大器，耦合在全差分放大器的正输入端和负输出端之间的第三电阻（“R3”）和耦合在负输入端和正输出端之间的第四电阻（“R4”）， 其中这些电阻的值由以下控制：相同的原理也可应用于差分到单端转换器。

公开(公告)号：US07577171B2

公开(公告)日：2009-08-18

申请号：US10361463

申请日：2003-02-10

Applicant: Mohammad Nejad ,  Guangming Yin ,  Ali Ghiasi

Inventor： Mohammad Nejad ,  Guangming Yin ,  Ali Ghiasi

IPC: H04J3/02

CPC classification number: H04L5/023 ,  H04L7/0008

Abstract: A multiple bit stream interface interfaces a first transmit data multiplexing integrated circuit and a second transmit data multiplexing integrated circuit. The multiple bit stream interface includes an interface plurality of transmit bit streams each of which carries a respective bit stream at an interface bit rate. The interface further includes a transmit data clock operating at a frequency corresponding to one-half of the interface bit rate. The first transmit data multiplexing integrated circuit receives a first plurality of transmit bit streams from a communication ASIC at a first bit rate. The second transmit data multiplexing integrated circuit produces a single bit stream output at a line bit rate. The interface plurality of transmit bit streams is divided into a first group and a second group, wherein the first group is carried on first group of lines and the second group is carried on a second group of lines. The transmit data clock is carried on a line that is centered with respect to the first group of lines and the second group of lines such that it resides between the first group of lines and the second group of lines. The interface may also interface a first receive data demultiplexing integrated circuit and a second receive data demultiplexing integrated circuit.

Abstract translation: 多比特流接口将第一发送数据多路复用集成电路和第二发送数据多路复用集成电路接口。 多比特流接口包括多个发送比特流的接口，每个发送比特流以接口比特率携带相应的比特流。 该接口还包括以对应于接口比特率的一半的频率工作的发送数据时钟。 第一发送数据复用集成电路以第一比特率从通信ASIC接收第一多个发送比特流。 第二发送数据复用集成电路以线路比特率产生单个比特流输出。 所述多个发送比特流的接口被分成第一组和第二组，其中所述第一组在第一组线路上承载，并且所述第二组在第二组线路上承载。 发送数据时钟在相对于第一组线路和第二组线路居中的线路上承载，使得它位于第一组线路组与第二组线路组之间。 接口还可以将第一接收数据解复用集成电路和第二接收数据解复用集成电路接口。

公开(公告)号：US07386084B2

公开(公告)日：2008-06-10

申请号：US10456803

申请日：2003-06-06

Applicant: Guangming Yin

Inventor： Guangming Yin

IPC: H04L7/00 ,  H04L25/00 ,  H04L25/40

CPC classification number: H03L7/091 ,  H03K5/135 ,  H04L7/033

Abstract: Aspects of the pattern-independent phase adjustment system includes a single output data XOR gate coupled to a differential input data signal and a bias voltage through a first variable resistor. A single output reference XOR gate may be coupled to a latched differential input signal and the bias voltage through a second variable resistor. At least one latch may be coupled to at least one differential input of the data and reference XOR gate. The single output of the data XOR gate may be a data output of a clock and data recovery circuit (CDR) and the single output of the reference XOR gate may be a reference output of the clock and CDR. No current may flow at the data output of the data XOR gate and the reference output of the reference XOR gate when there are no transitions occurring at an input of the phase detector.

Abstract translation: 独立于图形的相位调整系统的方面包括通过第一可变电阻器耦合到差分输入数据信号和偏置电压的单个输出数据XOR门。 单个输出参考XOR门可以通过第二可变电阻耦合到锁存的差分输入信号和偏置电压。 至少一个锁存器可以耦合到数据和参考XOR门的至少一个差分输入。 数据异或门的单个输出可以是时钟和数据恢复电路（CDR）的数据输出，并且参考异或门的单个输出可以是时钟和CDR的参考输出。 当在相位检测器的输入处没有发生转换时，数据XOR门的数据输出和参考XOR门的参考输出都不会流过电流。

公开(公告)号：US07346082B2

公开(公告)日：2008-03-18

申请号：US10361255

申请日：2003-02-10

Applicant: Ali Ghiasi ,  Mohammad Nejad ,  Guangming Yin

Inventor： Ali Ghiasi ,  Mohammad Nejad ,  Guangming Yin

IPC: H04J3/02

CPC classification number: H04J3/047 ,  H04J3/0685

Abstract: A multiple bit stream interface interfaces a first transmit data multiplexing integrated circuit and a second transmit data multiplexing integrated circuit. The multiple bit stream interface includes an interface plurality of transmit bit streams each of which carries a respective bit stream at an interface bit rate and in a natural order. The interface further includes a transmit data clock operating at a frequency corresponding to one-half of the interface bit rate. The first transmit data multiplexing integrated circuit receives a first plurality of transmit bit streams from a communication ASIC at a first bit rate. The second transmit data multiplexing integrated circuit produces a single bit stream output at a line bit rate. The interface plurality of transmit bit streams is divided into a first group and a second group, wherein the first group is carried on first group of lines and the second group is carried on a second group of lines. The transmit data clock is carried on a line that is centered with respect to the first group of lines and the second group of lines such that it resides between the first group of lines and the second group of lines. The interface may also interface a first receive data demultiplexing integrated circuit and a second receive data demultiplexing integrated circuit.

Abstract translation: 多比特流接口将第一发送数据多路复用集成电路和第二发送数据多路复用集成电路接口。 多比特流接口包括多个发送比特流的接口，每个发送比特流以接口比特率和自然顺序携带相应的比特流。 该接口还包括以对应于接口比特率的一半的频率工作的发送数据时钟。 第一发送数据复用集成电路以第一比特率从通信ASIC接收第一多个发送比特流。 第二发送数据复用集成电路以线路比特率产生单个比特流输出。 所述多个发送比特流的接口被分成第一组和第二组，其中所述第一组在第一组线路上承载，并且所述第二组在第二组线路上承载。 发送数据时钟在相对于第一组线路和第二组线路居中的线路上承载，使得它位于第一组线路组和第二组线路组之间。 接口还可以将第一接收数据解复用集成电路和第二接收数据解复用集成电路接口。

公开(公告)号：US20050248396A1

公开(公告)日：2005-11-10

申请号：US10841766

申请日：2004-05-07

Applicant: Mario Caresosa ,  Afshin Momtaz ,  Guangming Yin

Inventor： Mario Caresosa ,  Afshin Momtaz ,  Guangming Yin

IPC: H03F3/45 ,  H03G1/00

CPC classification number: H03G1/007 ,  H03F3/45188 ,  H03F3/45197 ,  H03F2203/45504 ,  H03F2203/45638 ,  H03G1/0029 ,  H03G1/0088

Abstract: An input processing circuit includes a first and second input transistors for receiving a differential pair of first and second input signals, respectively. At least one resistor is coupled between first terminals of the first and second input transistors. The input processing circuit includes a variable gain amplifier (VGA) circuit. At least one first transistor has a gate terminal, and is coupled between the first terminals of the first and second input transistors. At least one second transistor has a gate terminal, and is coupled between the first terminals of the first and second input transistors. A gate switch is coupled to the gate terminal of the at least one second transistor. The at least one first transistor and the at least one second transistor adjust a gain of the input processing circuit in response to a control voltage. The control voltage is applied to the gate terminal of the at least one first transistor, and the control voltage is applied to the gate terminal of the at least one second transistor through the gate switch.

Abstract translation: 输入处理电路包括分别用于接收第一和第二输入信号的差分对的第一和第二输入晶体管。 至少一个电阻耦合在第一和第二输入晶体管的第一端之间。 输入处理电路包括可变增益放大器（VGA）电路。 至少一个第一晶体管具有栅极端子，并且耦合在第一和第二输入晶体管的第一端子之间。 至少一个第二晶体管具有栅极端子，并且耦合在第一和第二输入晶体管的第一端子之间。 栅极开关耦合到至少一个第二晶体管的栅极端子。 所述至少一个第一晶体管和所述至少一个第二晶体管响应于控制电压调整所述输入处理电路的增益。 控制电压被施加到至少一个第一晶体管的栅极端子，并且通过栅极开关将控制电压施加到至少一个第二晶体管的栅极端子。

公开(公告)号：US20050218984A1

公开(公告)日：2005-10-06

申请号：US11133723

申请日：2005-05-20

Applicant: Guangming Yin

Inventor： Guangming Yin

IPC: H03D13/00 ,  H03F3/45 ,  H03K19/21 ,  H04L7/033

CPC classification number: H03D13/003 ,  H03K19/215 ,  H04L7/033

Abstract: Aspects of the invention provide a fast one level zero-current-state XOR gate. An embodiment of the invention provides a first pair of differentially configured transistors and a level shifting resistor coupled to the first pair of differentially configured transistors. The one level zero-current-state XOR gate may also include a second pair of differentially configured transistors. A core of the XOR gate may be coupled to outputs of the first and the second pairs of differentially configured transistors.

Abstract translation: 本发明的方面提供了快速的一级零电流状态异或门。 本发明的实施例提供了第一对差分配置的晶体管和耦合到第一对差分配置的晶体管的电平转换电阻器。 一级零电流状态XOR门还可以包括第二对差分配置的晶体管。 XOR门的核可以耦合到第一对和第二对差分配置的晶体管的输出。

公开(公告)号：US06754287B2

公开(公告)日：2004-06-22

申请号：US09814196

申请日：2001-03-21

Applicant: Paul A. Underbrink ,  Daryush Shamlou ,  Ricke W. Clark ,  Joseph H. Colles ,  Guangming Yin ,  Patrick D. Ryan ,  Kelly H. Hale

Inventor： Paul A. Underbrink ,  Daryush Shamlou ,  Ricke W. Clark ,  Joseph H. Colles ,  Guangming Yin ,  Patrick D. Ryan ,  Kelly H. Hale

IPC: H04L2720

CPC classification number: H03F3/217 ,  H03F2200/331 ,  H04L27/2046

Abstract: Communications systems, and particularly portable personal communications systems, such as portable phones, are becoming increasingly digital. One area that has remained largely analog, however, is the modulation and RF amplifier circuits. To produce a RF frequency waveform. An output of a class D amplifier is coupled to an integrator to create an analog signal. A resonant circuit shapes an output waveform based on the analog signal to create a sinusoidal RF broadcast signal. The waveform of the class D amplifier may be duty cycle modulated. Digital modulation may occur using a digital sigma delta modulator or a digital programmable divide modulator. Using the digital modulation techniques and class D amplification techniques together allows for broadcast a PSK signal that has been decomposed into amplitude and phase components.

Abstract translation: 通信系统，特别是诸如便携式电话的便携式个人通信系统正在变得越来越数字化。 然而，仍然是模拟的一个领域是调制和RF放大器电路。 产生RF频率波形。 D类放大器的输出耦合到积分器以产生模拟信号。 谐振电路基于模拟信号对输出波形进行整形以产生正弦RF广播信号。 D类放大器的波形可以是占空比调制的。 可以使用数字Σ-Δ调制器或数字可编程分频调制器进行数字调制。 一起使用数字调制技术和D类放大技术可以广播已经分解为幅度和相位分量的PSK信号。

公开(公告)号：US06535735B2

公开(公告)日：2003-03-18

申请号：US09814921

申请日：2001-03-22

Applicant: Paul A. Underbrink ,  Daryush Shamlou ,  Ricke W. Clark ,  Joseph H. Colles ,  Guangming Yin ,  Patrick D. Ryan ,  Kelly H. Hale

Inventor： Paul A. Underbrink ,  Daryush Shamlou ,  Ricke W. Clark ,  Joseph H. Colles ,  Guangming Yin ,  Patrick D. Ryan ,  Kelly H. Hale

IPC: H04Q720

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: Modern digital integrated circuits are commonly synchronized in their workings by clock circuits. The clock frequency for a circuit must take into account the propagation delay of signals within the critical path of the circuit. If the clock time is not adequate to allow propagation of signals through the critical path, improper circuit operation may result. The propagation delay is not a constant from circuit to circuit, and even in a single circuit may change due to temperature, power supply voltage and the like. Commonly, this variation is handled by assuming a worse case propagation delay of the critical path, and then designing the clock frequency and minimum power supply voltage of the circuit so that the circuit will function under worst case conditions. However, instead of assuming a worse case propagation delay of the critical path, the propagation delay may be measured in an actual circuit path that has been constructed to be the equivalent to, or slightly worse than, the propagation delay of the critical path. By knowing the actual worst case propagation delay, the circuit may be modified to operate with lower power supply voltages, conserving power and/or to controlling the frequency of the clock, so that the clock may be operated at or near the circuit's actual, not theoretical worst case limit. Such modifications of power supply voltage and/or clock frequency may occur during circuit operation and thus, adapt the circuit to the different operating parameters of each circuit.

公开(公告)号：US07864909B2

公开(公告)日：2011-01-04

申请号：US12613740

申请日：2009-11-06

Applicant: Jun Cao ,  Guangming Yin

Inventor： Jun Cao ,  Guangming Yin

IPC: H04L7/00

CPC classification number: G06F1/10 ,  H03K5/135 ,  H04J3/0629 ,  H04L7/0008 ,  H04L25/14

Abstract: A signal delay structure and method of reducing skew between clock and data signals in a high-speed serial communications interface includes making a global adjustment to the clock signal in the time domain to compensate for a component of the skew that is common between the clock and all data signals. This can include skew caused by the variation in frequency of the input clock from a nominal value, misalignment between the phase of the clock and data generated at the source of the two signals. The global adjustment is made through a delay component that is common to all of the clock signal lines for which skew with data signals is to be compensated. A second level adjustment is made that compensates for the component of the skew that is common to the clock and a subset of the data signals.

Abstract translation: 在高速串行通信接口中减少时钟和数据信号之间的偏差的信号延迟结构和方法包括对时域中的时钟信号进行全局调整，以补偿时钟和 所有数据信号。 这可能包括由输入时钟从标称值的频率变化引起的偏斜，时钟相位与在两个信号的源极产生的数据之间的偏移。 通过延迟分量进行全局调整，该延迟分量对于要对其进行补偿的具有数据信号的偏斜的所有时钟信号线是共同的。 进行第二级调整，补偿时钟共同的偏斜分量和数据信号的子集。

公开(公告)号：US07834790B1

公开(公告)日：2010-11-16

申请号：US12206773

申请日：2008-09-09

Applicant: Guangming Yin

Inventor： Guangming Yin

IPC: H03M1/66

CPC classification number: H03M1/002 ,  H03M1/66

Abstract: A communication device includes a communication port that includes a digital to analog converter (DAC) that may be configured to output for transmission an analog signal that corresponds to a digital input such as link data that is to be transmitted on a physical link. The communication port further includes a control unit coupled to the DAC and may be configured to provide a bias current to the DAC during operation. In addition, the control unit may further be configured to reduce the bias current to the DAC dependent upon a mode of operation of the communication port and whether there is data to transmit.

Abstract translation: 通信设备包括通信端口，其包括数模转换器（DAC），其可以被配置为输出用于传输对应于数字输入的模拟信号，例如要在物理链路上传输的链路数据。 通信端口还包括耦合到DAC的控制单元，并且可以被配置为在操作期间向DAC提供偏置电流。 此外，控制单元还可以被配置为根据通信端口的操作模式以及是否存在要发送的数据来减小到DAC的偏置电流。