Method and apparatus for the compensation of an additive signal in a data signal
    41.
    发明授权
    Method and apparatus for the compensation of an additive signal in a data signal 失效
    用于补偿数据信号中的附加信号的方法和装置

    公开(公告)号:US06219192B1

    公开(公告)日:2001-04-17

    申请号:US09179148

    申请日:1998-10-26

    Abstract: The method and apparatus have application to the compensation of transient signals produced on reading a data storage device with a magneto-resistive head due to thermal contact with asperities on the data storage medium. Preferably, the data channel employs partial-response maximum-likelihood detection. The method compensates for an additive signal in a data signal and comprises the steps of: detecting the contribution to said data signal by said additive signal; initially compensating the data signal by maintaining a DC offset in said data signal, the initial level of said DC offset being set in dependence on the detected contribution; and while compensating the data signal, detecting when the compensated data signal exceeds a predetermined threshold and varying the set level of said DC offset in dependence upon said detection.

    Abstract translation: 该方法和装置可应用于由于与数据存储介质上的粗糙度的热接触而使用磁阻头读取数据存储装置时产生的瞬态信号的补偿。 优选地,数据信道采用部分响应最大似然检测。该方法补偿数据信号中的加法信号,并且包括以下步骤:通过所述加法信号检测对所述数据信号的贡献; 通过维持所述数据信号中的DC偏移来初始地补偿数据信号,根据检测到的贡献来设置所述DC偏移的初始电平; 并且在补偿数据信号的同时,检测补偿数据信号何时超过预定阈值,并根据所述检测改变所述DC偏移的设定电平。

    Method for planarizing high step-height integrated circuit structures
    42.
    发明授权
    Method for planarizing high step-height integrated circuit structures 失效
    平面化高步高集成电路结构的方法

    公开(公告)号:US5674773A

    公开(公告)日:1997-10-07

    申请号:US616897

    申请日:1996-03-15

    CPC classification number: H01L21/31051

    Abstract: A method for planarizing a high step-height integrated circuit structure within an integrated circuit. There is first formed upon a semiconductor substrate a high step-height integrated circuit structure. Formed then adjoining the high step-height integrated circuit structure is a patterned Global Planarization Dielectric (GPD) layer. There is then formed upon the exposed surfaces of the semiconductor substrate, the high step-height integrated circuit structure and the patterned Global Planarization Dielectric (GPD) layer a reflowable dielectric layer. Finally, the reflowable dielectric layer is reflowed.

    Abstract translation: 一种用于在集成电路内平坦化高阶高度集成电路结构的方法。 首先在半导体衬底上形成高步高集成电路结构。 形成,然后毗邻高步高集成电路结构是一个图案化的全球平面介电(GPD)层。 然后形成在半导体衬底的暴露表面,高阶高度集成电路结构和图案化全局平面化电介质(GPD)层的可回流电介质层上。 最后,可回流介电层被回流。

    Multiple exposure method for photo-exposing photosensitive layers upon
high step height topography substrate layers
    43.
    发明授权
    Multiple exposure method for photo-exposing photosensitive layers upon high step height topography substrate layers 失效
    在高阶高度地形基底层上曝光感光层的多重曝光方法

    公开(公告)号:US5631112A

    公开(公告)日:1997-05-20

    申请号:US726033

    申请日:1996-10-07

    CPC classification number: G03F7/70475 G03F7/2022

    Abstract: A method for photo-exposing a blanket conformal photosensitive layer upon a high step height topography substrate layer. There is first provided a high step height topography substrate layer having a blanket conformal photosensitive layer formed thereupon. The high step height topography substrate layer has a first region having a first step height separated from a third region having a third step height by a second region having a second step height. The second step height is intermediate to the first step height and the third step height. The blanket conformal photosensitive layer is photo-exposed to form a first pattern upon the first region and the second region through use of a first reticle and a first photo-exposure condition. The first photo-exposure condition provides a first depth of focus suitable for at least the first region. In a separate process step, the blanket conformal photosensitive layer is photo-exposed to form a second pattern upon the second region and the third region through use of a second reticle and a second photo-exposure condition. The second photo-exposure condition provides a second depth of focus suitable for at least the third region. The first pattern upon the second region and the second pattern upon the second region overlap.

    Abstract translation: 一种用于在高阶高度地形衬底层上曝光毯状保形感光层的方法。 首先提供了具有在其上形成的覆盖层保形感光层的高阶高度地形基底层。 高台阶高度地形基底层具有第一区域,第一区域具有与具有第三台阶高度的第三区域分离的第一台阶高度与具有第二台阶高度的第二区域。 第二步高度处于第一步高度和第三步高度的中间。 通过使用第一掩模版和第一光曝光条件,在第一区域和第二区域上曝光毯状保形感光层以形成第一图案。 第一曝光条件提供适于至少第一区域的第一焦点深度。 在单独的工艺步骤中,通过使用第二掩模版和第二曝光条件,在第二区域和第三区域上曝光毯状保形光敏层以形成第二图案。 第二曝光条件提供适于至少第三区域的第二焦点深度。 第二区域上的第一图案和第二区域上的第二图案重叠。

    Curtain opener
    44.
    外观设计

    公开(公告)号:USD1053603S1

    公开(公告)日:2024-12-10

    申请号:US29871577

    申请日:2023-02-23

    Applicant: Bin Liu

    Designer: Bin Liu

    Spinning top toy
    45.
    外观设计

    公开(公告)号:USD963755S1

    公开(公告)日:2022-09-13

    申请号:US29817319

    申请日:2021-11-30

    Applicant: Bin Liu

    Designer: Bin Liu

    Plant stand
    46.
    外观设计

    公开(公告)号:USD951671S1

    公开(公告)日:2022-05-17

    申请号:US29787621

    申请日:2021-06-08

    Applicant: Bin Liu

    Designer: Bin Liu

    NANOWIRE STRUCTURES FOR SOLAR WATER SPLITTING

    公开(公告)号:US20190024246A1

    公开(公告)日:2019-01-24

    申请号:US14692886

    申请日:2015-04-22

    Abstract: This disclosure provides systems, methods, and apparatus related to solar water splitting. In one aspect, a structure includes a plurality of first nanowires, the plurality of first nanowires comprising an n-type semiconductor or a p-type semiconductor. The structure further includes a second nanowire, the second nanowire comprising the n-type semiconductor or the p-type semiconductor, the second nanowire being a different composition than the plurality of first nanowires. The second nanowire includes a first region and a second region, with the first region having a conductive layer disposed thereon, and each of the plurality of first nanowires being disposed on the conductive layer.

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