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190 条记录 (耗时 0.031 秒)

    Method for planarizing high step-height integrated circuit structures
    1.
    发明授权
    Method for planarizing high step-height integrated circuit structures 失效
    平面化高步高集成电路结构的方法

    公开(公告)号：US5674773A

    公开(公告)日：1997-10-07

    申请号：US616897

    申请日：1996-03-15

    申请人： Chao-Ming Koh ,  Bin Liu

    发明人： Chao-Ming Koh ,  Bin Liu

    IPC分类号： H01L21/3105 ,  H01L21/70

    CPC分类号： H01L21/31051

    摘要： A method for planarizing a high step-height integrated circuit structure within an integrated circuit. There is first formed upon a semiconductor substrate a high step-height integrated circuit structure. Formed then adjoining the high step-height integrated circuit structure is a patterned Global Planarization Dielectric (GPD) layer. There is then formed upon the exposed surfaces of the semiconductor substrate, the high step-height integrated circuit structure and the patterned Global Planarization Dielectric (GPD) layer a reflowable dielectric layer. Finally, the reflowable dielectric layer is reflowed.

    摘要翻译： 一种用于在集成电路内平坦化高阶高度集成电路结构的方法。 首先在半导体衬底上形成高步高集成电路结构。 形成，然后毗邻高步高集成电路结构是一个图案化的全球平面介电（GPD）层。 然后形成在半导体衬底的暴露表面，高阶高度集成电路结构和图案化全局平面化电介质（GPD）层的可回流电介质层上。 最后，可回流介电层被回流。

    Method of manufacturing a crown shape capacitor in semiconductor memory using a single step etching
    2.
    发明授权
    Method of manufacturing a crown shape capacitor in semiconductor memory using a single step etching 失效
    使用单步蚀刻在半导体存储器中制造冠状电容器的方法

    公开(公告)号：US5804489A

    公开(公告)日：1998-09-08

    申请号：US679196

    申请日：1996-07-12

    申请人： Fu-Liang Yang ,  Erik S. Jeng ,  Yu-Chun Ho ,  Bin Liu ,  Chao-Ming Koh

    发明人： Fu-Liang Yang ,  Erik S. Jeng ,  Yu-Chun Ho ,  Bin Liu ,  Chao-Ming Koh

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10852 ,  H01L27/10817

    摘要： The present invention is a method of manufacturing crown shape capacitors in the semiconducter memories. Using a single step etching to farbricate the capacitor in a DRAM cell. The method can form side wall polymers and etching byproductions on the surface of the first polysilicon, using the side wall polymers and the etching byproductions as a mask to form the crown shape capacitors with pillars. Moreover, this present invention can form the crown shape structure and pillars in the same step, the crown shape structure and the pillars increase the surface area of the capacitor. Therefore the present invention will increase the performance of the capacitor.

    摘要翻译： 本发明是在半导体存储器中制造冠状电容器的方法。 使用单步蚀刻来超越DRAM单元中的电容器。 该方法可以使用侧壁聚合物和蚀刻副产物作为掩模形成侧壁聚合物并在第一多晶硅的表面上蚀刻副产物，以形成具有支柱的冠状电容器。 此外，本发明可以在相同的步骤中形成冠状结构和柱，冠状结构和柱增加电容器的表面积。 因此，本发明将增加电容器的性能。

    Method of manufacturing a stacked capacitor having a fin-shaped storage electrode on a dynamic random access memory cell
    3.
    发明授权
    Method of manufacturing a stacked capacitor having a fin-shaped storage electrode on a dynamic random access memory cell 失效
    制造在动态随机存取存储单元上具有鳍状存储电极的层叠电容器的方法

    公开(公告)号：US5807782A

    公开(公告)日：1998-09-15

    申请号：US533566

    申请日：1995-09-25

    申请人： Chao-Ming Koh ,  Wen-Jya Liang ,  Bin Liu

    发明人： Chao-Ming Koh ,  Wen-Jya Liang ,  Bin Liu

    IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

    CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/87 ,  H01L28/88

    摘要： A method for manufacturing a stacked capacitor having fin-shaped electrodes with increased capacitance on a dynamic random access memory (DRAM) cell, was achieved. The invention eliminates the need for a silicon nitride etch stop layer, which is known to cause stress in the substrate and lead to defects. The capacitor bottom electrodes having fin shaped portions is fabricated by depositing a multilayer of alternate layers of silicon oxide and doped polysilicon on a partially completed DRAM device having FETs. After forming, with single masking step, the node contacts to the substrate in the multilayer and depositing another doped polysilicon layer, the polysilicon layers and oxide layer are patterned to form the electrodes. An important feature of this invention is that the patterned multilayer is etched to the silicon oxide layer over the bottom polysilicon layer and then the silicon oxide layer(s) are isotropically etched (e.g. in HF) to form the fin capacitor. The fin structure is then used as a mask to anisotropically etch the bottom polysilicon layer, and thereby complete and electrically isolate the bottom fin-shaped electrodes. The capacitor is completed by forming the inter-electrode dielectric and depositing a top electrode layer.

    摘要翻译： 实现了在动态随机存取存储器（DRAM）单元上制造具有增加电容的鳍状电极的堆叠电容器的方法。 本发明消除了氮化硅蚀刻停止层的需要，其已知会在衬底中引起应力并导致缺陷。 具有鳍形部分的电容器底部电极通过在具有FET的部分完成的DRAM器件上沉积多层氧化硅和掺杂多晶硅的交替层来制造。 在形成之后，通过单个掩模步骤，节点接触多层中的衬底并沉积另一个掺杂多晶硅层，对多晶硅层和氧化物层进行构图以形成电极。 本发明的一个重要特征是，图案化多层被蚀刻到底部多晶硅层上的氧化硅层上，然后氧化硅层被各向同性地蚀刻（例如在HF中）以形成散热片电容器。 然后将鳍结构用作掩模以各向异性蚀刻底部多晶硅层，从而完成并电隔离底部鳍状电极。 通过形成电极间电介质并沉积顶部电极层来完成电容器。

    Spinning top toy
    4.
    外观设计
    Spinning top toy 有权

    公开(公告)号：USD963755S1

    公开(公告)日：2022-09-13

    申请号：US29817319

    申请日：2021-11-30

    申请人： Bin Liu

    设计人： Bin Liu

    Plant stand
    5.
    外观设计
    Plant stand 有权

    公开(公告)号：USD951671S1

    公开(公告)日：2022-05-17

    申请号：US29787621

    申请日：2021-06-08

    申请人： Bin Liu

    设计人： Bin Liu

    NANOWIRE STRUCTURES FOR SOLAR WATER SPLITTING
    8.
    发明申请
    NANOWIRE STRUCTURES FOR SOLAR WATER SPLITTING 审中-公开

    公开(公告)号：US20190024246A1

    公开(公告)日：2019-01-24

    申请号：US14692886

    申请日：2015-04-22

    申请人： Peidong Yang ,  Chong Liu ,  Jinyao Tang ,  Hao Ming Chen ,  Bin Liu

    发明人： Peidong Yang ,  Chong Liu ,  Jinyao Tang ,  Hao Ming Chen ,  Bin Liu

    IPC分类号： C25B1/00 ,  C25B1/04 ,  H01G9/20 ,  C25B11/02 ,  C25B11/04

    摘要： This disclosure provides systems, methods, and apparatus related to solar water splitting. In one aspect, a structure includes a plurality of first nanowires, the plurality of first nanowires comprising an n-type semiconductor or a p-type semiconductor. The structure further includes a second nanowire, the second nanowire comprising the n-type semiconductor or the p-type semiconductor, the second nanowire being a different composition than the plurality of first nanowires. The second nanowire includes a first region and a second region, with the first region having a conductive layer disposed thereon, and each of the plurality of first nanowires being disposed on the conductive layer.

    Mercury-free lead-free button battery
    10.
    发明授权
    Mercury-free lead-free button battery 有权
    无汞无铅纽扣电池

    公开(公告)号：US09490498B2

    公开(公告)日：2016-11-08

    申请号：US14361703

    申请日：2011-11-30

    申请人： Bin Liu

    发明人： Bin Liu

    IPC分类号： H01M10/04 ,  H01M2/14 ,  H01M2/02 ,  H01M2/04 ,  H01M2/12

    CPC分类号： H01M10/0427 ,  H01M2/0222 ,  H01M2/0287 ,  H01M2/0413 ,  H01M2/12 ,  H01M2/14

    摘要： A mercury-free lead-free button battery includes a negative cap, a cathode material, a gasket ring, a positive can, an anode material, and a diaphragm. The positive can and the negative cap are combined. The gasket ring is clamped between the positive can and the negative cap for separating the positive can from the negative cap. The cathode material is arranged on the bottom of the positive can. The diaphragm is arranged on the cathode material. The anode material is arranged between the negative cap and the diaphragm. A partition unit is arranged between the negative cap and the anode material for separating the anode material from the negative cap and conductively connecting the anode material and the negative cap. The partition unit ensures disconnection between the anode material and the negative cap and therefore safety of the battery by preventing expansion, weeping and even that would otherwise happen.

    摘要翻译： 无汞无铅纽扣电池包括负极帽，阴极材料，垫圈，正极罐，阳极材料和隔膜。 积极的可以和负的帽子结合在一起。 垫圈环夹在正盖和负盖之间，用于将正盖与负盖分离。 正极材料布置在正极罐的底部。 隔膜布置在阴极材料上。 负极材料布置在负极盖和隔膜之间。 分隔单元布置在负盖和阳极材料之间，用于将阳极材料与负极帽分离，并导电连接阳极材料和负极盖。 分隔单元确保阳极材料和负极帽之间的断开，因此通过防止膨胀而发生电池的安全，否则会发生哭泣。