Processes for producing tunable optical cavities
    41.
    发明授权
    Processes for producing tunable optical cavities 有权
    用于生产可调谐光腔的工艺

    公开(公告)号:US08120782B2

    公开(公告)日:2012-02-21

    申请号:US12603627

    申请日:2009-10-22

    IPC分类号: G01B9/02

    摘要: A tunable optical cavity can be tuned by relative movement between two reflection surfaces, such as by deforming elastomer spacers connected between mirrors or other light-reflective components that include the reflection surfaces. The optical cavity structure includes an analyte region in its light-transmissive region, and presence of analyte in the analyte region affects output light when the optical cavity is tuned to a set of positions. Electrodes that cause deformation of the spacers can also be used to capacitively sense the distance between them. Control circuitry that provides tuning signals can cause continuous movement across a range of positions, allowing continuous photosensing of analyte-affected output light by a detector.

    摘要翻译: 可调光学腔可以通过两个反射表面之间的相对运动进行调节,例如通过变形连接在反射镜之间的弹性体隔离物或包括反射表面的其它光反射部件。 光腔结构包括其透光区域中的分析物区域,并且当光学腔被调谐到一组位置时,分析物区域中的分析物的存在影响输出光。 导致间隔物变形的电极也可用于电容地感测它们之间的距离。 提供调谐信号的控制电路可以在一定范围的位置上引起连续的运动,从而允许由检测器对被分析物影响的输出光进行持续的光敏。

    Method for decimation of images
    42.
    发明授权
    Method for decimation of images 有权
    抽取图像的方法

    公开(公告)号:US08079656B2

    公开(公告)日:2011-12-20

    申请号:US11644238

    申请日:2006-12-22

    IPC分类号: B41J29/38 G06K9/36 G06F17/17

    摘要: In the case of printing at high addressability, where the cell size is smaller than the spot size, an image can be decimated in a manner that will limit the large accumulation of printed material. The proper decimation of the image will depend on the spot size, the physics of drop coalescence and the addressability during printing. A simple method of using concentric decimation is disclosed herein to enable this process.

    摘要翻译: 在高可寻址性的情况下,其中单元尺寸小于点尺寸,可以以限制印刷材料的大量积累的方式对图像进行抽取。 图像的正确抽取将取决于斑点大小,下落聚结的物理学和打印期间的寻址能力。 本文公开了一种使用同心抽取的简单方法来实现该过程。

    Method of printing with high spot placement accuracy
    43.
    发明授权
    Method of printing with high spot placement accuracy 有权
    打印精度高的方法

    公开(公告)号:US07926900B2

    公开(公告)日:2011-04-19

    申请号:US11644129

    申请日:2006-12-22

    IPC分类号: B41J29/393

    摘要: A method of printing spots with high spot placement accuracy using print heads with random/unevenly spaced ejector locations and coarse alignment of the multiple print heads. This is performed by accurately determining the spot positions from all the print heads using a vision system and printing at high addressability. The spot placement accuracy will be determined by the addressability as long as the ejected drop position is reproducible and other system errors are negligible.

    摘要翻译: 使用具有随机/不均匀间隔的喷射器位置的打印头和多个打印头的粗略对准来打印具有高点放置精度的斑点的方法。 这是通过使用视觉系统精确地确定来自所有打印头的点位置并以高可寻址性进行打印来执行的。 点位置精度将由可寻址性决定,只要弹出的下降位置是可重复的,并且其他系统错误可以忽略不计。

    METHOD FOR DECIMATION OF IMAGES
    44.
    发明申请

    公开(公告)号:US20110087717A1

    公开(公告)日:2011-04-14

    申请号:US12913825

    申请日:2010-10-28

    IPC分类号: G06F17/17

    摘要: In the case of printing at high addressability, where the cell size is smaller than the spot size, an image can be decimated in a manner that will limit the large accumulation of printed material. The proper decimation of the image will depend on the spot size, the physics of drop coalescence and the addressability during printing. A simple method of using concentric decimation is disclosed herein to enable this process.

    METAL PATTERNING FOR ELECTRICALLY CONDUCTIVE STRUCTURES BASED ON ALLOY FORMATION
    45.
    发明申请
    METAL PATTERNING FOR ELECTRICALLY CONDUCTIVE STRUCTURES BASED ON ALLOY FORMATION 审中-公开
    基于合金形成的导电结构的金属图案

    公开(公告)号:US20100294352A1

    公开(公告)日:2010-11-25

    申请号:US12469101

    申请日:2009-05-20

    摘要: Layered metal structures are patterned to form a surface with some locations having an alloy along the top surface at some locations and the original top metal layer at other locations along the surface. The alloy and original top metal layer can be selected to have differential etching properties such that the pattern of the alloy or original metal can be selectively etched to form a patterned metal interconnect. In general, the patterning is performed by localized heating that drives formation of the alloy at the heated locations. The metal patterning can be useful for solar cell applications as well as for electronics applications, such as display applications.

    摘要翻译: 层状金属结构被图案化以形成表面,其中一些位置在某些位置处具有沿着顶表面的合金,并且沿表面的其它位置具有原始顶部金属层。 可以选择合金和原始顶部金属层以具有差异蚀刻性质,使得可以选择性地蚀刻合金或原始金属的图案以形成图案化的金属互连。 通常,图案化是通过局部加热进行的,其驱动在加热位置形成合金。 金属图案化可用于太阳能电池应用以及电子应用,例如显示器应用。

    Tuning optical cavities
    46.
    发明授权
    Tuning optical cavities 有权
    调谐光腔

    公开(公告)号:US07817281B2

    公开(公告)日:2010-10-19

    申请号:US11702320

    申请日:2007-02-05

    IPC分类号: G01B9/02

    摘要: An inhomogeneous optical cavity is tuned by changing its shape, such as by changing reflection surface positions to change tilt angle, thickness, or both. Deformable components such as elastomer spacers can be connected so that, when deformed, they change relative positions of structures with light-reflective components such as mirrors, changing cavity shape. Electrodes can cause deformation, such as electrostatically, electromagnetically, or piezoelectrically, and can also be used to measure thicknesses of the cavity. The cavity can be tuned, for example, across a continuous spectrum, to a specific wavelength band, to a shape that increases or decreases the number of modes it has, to a series of transmission ranges each suitable for a respective light source, with a modulation that allows lock-in with photosensing for greater sensitivity, and so forth. The optical cavity can be a linear variable filter fabricated on the photosensitive surface of a photosensing component such as a photosensor array or a position-sensitive detector.

    摘要翻译: 通过改变其形状来调整不均匀的光学腔,例如通过改变反射面位置来改变倾斜角,厚度或两者。 变形部件如弹性体间隔件可以连接,使得当变形时,它们改变结构与诸如反射镜的光反射部件的相对位置,改变腔体形状。 电极可能导致变形,例如静电,电磁或压电,也可用于测量腔的厚度。 空腔可以例如通过连续光谱被调谐到特定波长带,以使其具有的模式数量增加或减少的形状调整到各自适用于相应光源的一系列传输范围,其中 允许通过光敏锁定来实现更高灵敏度的调制,等等。 光腔可以是制造在诸如光电传感器阵列或位置敏感检测器的感光部件的感光表面上的线性可变滤波器。

    Global bit line restore timing scheme and circuit
    47.
    发明授权
    Global bit line restore timing scheme and circuit 失效
    全局位线恢复时序方案和电路

    公开(公告)号:US07170774B2

    公开(公告)日:2007-01-30

    申请号:US11054479

    申请日:2005-02-09

    IPC分类号: G11C11/00

    CPC分类号: G11C7/18 G11C7/12 G11C11/417

    摘要: A domino SRAM array restore pulse generation system launches the word decode line by the same local clock as the restore pulse, thus eliminating any race issues with the word line select. This system allows the global bit select (or column select) to have fast activation by releasing the reset signal (with the earliest arriving array clock, ckl), while guaranteeing almost perfect tracking with the bit decode system. This allows for the widest possible write window; earliest release of the pre-charge in the global column select, and resetting only after the bit decode system is deactivated.

    摘要翻译: 多米诺SRAM阵列恢复脉冲发生系统通过与恢复脉冲相同的本地时钟启动字解码线,从而消除了字线选择的任何种族问题。 该系统允许全局位选择(或列选择)通过释放复位信号(具有最早到达的阵列时钟ckl)来快速激活,同时保证与位解码系统几乎完美的跟踪。 这允许最广泛的写入窗口; 全局列中最早发布预充电选择,仅在位解码系统被禁用后进行复位。

    SRAM ring oscillator
    48.
    发明授权
    SRAM ring oscillator 有权
    SRAM环形振荡器

    公开(公告)号:US07142064B2

    公开(公告)日:2006-11-28

    申请号:US10973366

    申请日:2004-10-26

    IPC分类号: H03K3/03 G01R23/00 G01R31/26

    摘要: An SRAM design evaluation circuit topology has the gates of the SRAM cell pass Gate Field Effect Transistors (FETs) connected to the cross-coupled gates of the inverter pair of the SRAM cell. This evaluation circuit typology is used in a full cell implementation. A series of full cells are interconnected one to another in a loop to form a ring oscillator. The output of the ring is frequency divided and measured to study the read and write behavior of the cell design. Similarly, half-cells, with the gates of their pass gates grounded, are interconnected one to another to form a ring oscillator, the output of which is frequency divided and measured to help isolate pass gate impact on memory function. The modified SRAM cell topology, connected as a ring oscillator in hardware, can be used to fully characterize an SRAM cell design, without the use of peripheral read/write circuitry.

    摘要翻译: SRAM设计评估电路拓扑结构具有连接到SRAM单元的反相器对的交叉耦合栅极的SRAM单元通过栅极场效应晶体管(FET)的栅极。 该评估电路类型用于全单元实现。 一系列完整的单元在一个环路中互相连接形成一个环形振荡器。 环的输出被分频和测量,以研究单元设计的读写行为。 类似地,其通路门的栅极接地的半电池互相互连以形成环形振荡器,其输出被分频和测量,以帮助隔离通道对存储器功能的影响。 作为硬件环形振荡器连接的修改后的SRAM单元拓扑可用于完全表征SRAM单元设计,而无需使用外设读/写电路。

    Optical beam position active sensing and control using satellite beams
    49.
    发明授权
    Optical beam position active sensing and control using satellite beams 有权
    使用卫星光束的光束位置主动感测和控制

    公开(公告)号:US07116613B2

    公开(公告)日:2006-10-03

    申请号:US10443184

    申请日:2003-05-22

    IPC分类号: G11B5/09

    摘要: A beam position control system controls a position of a beam directed from a beam source. The beam position control system includes a beam position sensing system that generates one or more satellite beams which are used to determine the position of a main beam. A beam offset computation block determines a relative position of the main beam with respect to a desired main beam position and provides beam offset information to a controller that generates a compensation signal used to adjust the main beam position to the desired main beam position via a beam actuation system.

    摘要翻译: 光束位置控制系统控制从光束源引导的光束的位置。 波束位置控制系统包括波束位置检测系统,其产生用于确定主波束位置的一个或多个卫星波束。 波束偏移计算块确定主波束相对于期望的主波束位置的相对位置,并将波束偏移信息提供给控制器,该控制器产生用于经由波束将主波束位置调整到期望主波束位置的补偿信号 驱动系统。

    High performance CMOS NOR predecode circuit
    50.
    发明申请
    High performance CMOS NOR predecode circuit 审中-公开
    高性能CMOS NOR预解码电路

    公开(公告)号:US20060176757A1

    公开(公告)日:2006-08-10

    申请号:US11054147

    申请日:2005-02-09

    IPC分类号: G11C8/00

    CPC分类号: G11C8/10

    摘要: A CMOS decoder with an FET stack coupled to the input node so that when all the inputs are selected, the FET stack is conducting and initially holds the value on the input node, and prevents dipping of the input node voltage.

    摘要翻译: 具有耦合到输入节点的FET堆叠的CMOS解码器,使得当选择所有输入时,FET堆栈正在导通,并且初始地保持输入节点上的值,并且防止输入节点电压的浸入。