公开(公告)号：US08497721B1

公开(公告)日：2013-07-30

申请号：US13160569

申请日：2011-06-15

申请人： Hamid Partovi ,  Alfred Yeung ,  John Ngai ,  Ronen Cohen

发明人： Hamid Partovi ,  Alfred Yeung ,  John Ngai ,  Ronen Cohen

IPC分类号： H03K3/289

CPC分类号： H03K3/356156

摘要： A latch device is provided with a relay and a shadow latch. The relay has an input to accept a binary relay input signal, an input to accept a clock signal, an input to accept a shadow-Q signal, and an output to supply a binary Q signal value equal to the relay input signal value. The relay output is supplied in response to the relay input signal, the shadow-Q signal, and the clock signal. The shadow latch has an input to accept the relay input signal, an input to accept the clock signal, and an output to supply the shadow-Q signal with a value equal to an inverted Q signal value. The shadow latch output is supplied in response to the relay input signal and clock signal.

摘要翻译： 闩锁装置设置有继电器和阴影闩锁。 继电器具有接受二进制继电器输入信号的输入端，接收时钟信号的输入端，接收阴影Q信号的输入端和提供等于继电器输入信号值的二进制Q信号值的输出端。 响应于继电器输入信号，阴影-Q信号和时钟信号提供继电器输出。 阴影锁存器具有用于接受继电器输入信号的输入端，用于接受时钟信号的输入端，以及用于向shadow-Q信号提供等于反相Q信号值的值的输出端。 响应于继电器输入信号和时钟信号提供阴影锁存输出。

公开(公告)号：US08421514B1

公开(公告)日：2013-04-16

申请号：US13225044

申请日：2011-09-02

申请人： Alfred Yeung ,  Hamid Partovi ,  Luca Ravezzi ,  John Ngai

发明人： Alfred Yeung ,  Hamid Partovi ,  Luca Ravezzi ,  John Ngai

IPC分类号： H03K3/289

CPC分类号： H03K3/013 ,  H03K3/356156 ,  H03K3/35625

摘要： A hazard-free minimal-latency flip-flop (HFML-FF) is provided. A master latch includes an input to accept a D1 signal, an input to accept a clock signal, an input to accept an inverted shadow-D2 signal, and an output to supply a D2 signal. The master latch has an input to accept a shadow-D1 signal, an input to accept the clock signal, and an output to supply a shadow-D2 signal and the inverted shadow-D2 signal. The slave latch has an input to accept the D2 signal, an input to accept the clock signal, an input to accept an inverted shadow-Q signal, and an output to supply a Q signal. The slave latch has an input to accept either the D2 signal or the shadow-D2 signal, an input to accept the clock signal, and an output to supply a shadow-Q signal and the inverted shadow-Q signal. The design may use clocked inverters or pass gates.

摘要翻译： 提供无危险的最小延迟触发器（HFML-FF）。 主锁存器包括接收D1信号的输入端，接受时钟信号的输入端，接收反相阴影D2信号的输入端和提供D2信号的输出端。 主锁存器具有接受阴影D1信号的输入端，接受时钟信号的输入端，以及提供阴影D2信号和反相阴影D2信号的输出端。 从锁存器具有接收D2信号的输入端，接受时钟信号的输入端，接收反相阴影Q信号的输入端和提供Q信号的输出端。 从锁存器具有接收D2信号或阴影D2信号的输入端，用于接受时钟信号的输入端和用于提供阴影Q信号和反相阴影Q信号的输出。 该设计可以使用时钟反相器或通过门。

公开(公告)号：US07991573B2

公开(公告)日：2011-08-02

申请号：US11960069

申请日：2007-12-19

申请人： Russell Homer ,  Luca Ravezzi ,  Hamid Partovi

发明人： Russell Homer ,  Luca Ravezzi ,  Hamid Partovi

IPC分类号： G01R35/00

CPC分类号： G11C7/1051 ,  G11C7/02 ,  G11C7/1057 ,  G11C29/02 ,  G11C29/022 ,  G11C29/50008 ,  G11C2207/2254

摘要： One embodiment provides an integrated circuit including a first circuit, a second circuit, and a third circuit. The first circuit is configured to provide a calibrated signal. The second circuit is configured to low pass filter the calibrated signal and provide a filtered calibrated signal. The third circuit is configured to provide a control signal and store the control signal based on the filtered calibrated signal. The third circuit averages stored controlled signals to provide a calibration result.

摘要翻译： 一个实施例提供了包括第一电路，第二电路和第三电路的集成电路。 第一电路被配置为提供校准信号。 第二电路被配置为对经校准的信号进行低通滤波并提供滤波的校准信号。 第三电路被配置为提供控制信号并且基于滤波的校准信号来存储控制信号。 存储控制信号的第三个电路平均提供校准结果。

公开(公告)号：US20110012685A1

公开(公告)日：2011-01-20

申请号：US12684164

申请日：2010-01-08

申请人： Hamid Partovi ,  Luca Ravezzi

发明人： Hamid Partovi ,  Luca Ravezzi

IPC分类号： H03K3/03

CPC分类号： H03K3/0315

摘要： A voltage controlled oscillator circuit includes first and second power rails, a control voltage rail, an input terminal, and an output terminal. A plurality of domino stages are series connected in a ring, with each of the domino stages being connected across the first and second power rails and being responsive to the control voltage rail. A plurality of feedback paths is provided with each path connected to enable one of the plurality of domino stages to input a feedback output signal to a preceding serially connected domino stage. A reset signal is asserted to place the domino stages in a post charge state and deasserted to allow the domino stages to begin producing an oscillating signal.

摘要翻译： 压控振荡器电路包括第一和第二电源轨，控制电压轨，输入端和输出端。 多个多米诺骨牌级串联连接在一个环中，其中每个多米诺骨牌级跨越第一和第二电力轨道连接并响应控制电压轨。 提供多个反馈路径，每个路径被连接以使得多个多米诺骨牌阶段中的一个能够将反馈输出信号输入到先前的串行连接的多米诺骨牌阶段。 复位信号被断言以将多米诺骨牌阶段置于后付费状态，并且被断言以允许多米诺骨牌阶段开始产生振荡信号。

公开(公告)号：US20050193301A1

公开(公告)日：2005-09-01

申请号：US10786879

申请日：2004-02-25

申请人： Hamid Partovi ,  William Evans

发明人： Hamid Partovi ,  William Evans

IPC分类号： G01R31/28 ,  H03L7/06 ,  H04L7/00 ,  H04L7/033

CPC分类号： H03L7/06 ,  H04L7/0091

摘要： A clock signal can be synthesized by performing a clock and data recovery (CDR) operation on a potentially noisy clock source signal which has a known transition density. The CDR operation produces a desired clock signal in response to the clock source signal. In order to reduce crosstalk between plesiochronous receive and transmit clock domains of a serial data transceiver, a single common PLL is used both to recover the receive clock from the received data and to synthesize the transmit clock from a potentially noisy transmit clock source signal.

摘要翻译： 可以通过对具有已知转换密度的潜在噪声时钟源信号执行时钟和数据恢复（CDR）操作来合成时钟信号。 CDR操作响应于时钟源信号产生期望的时钟信号。 为了减少串行数据收发器的同步接收和发送时钟域之间的串扰，使用单个公共PLL来从接收到的数据恢复接收时钟，并从潜在的噪声发射时钟源信号合成发送时钟。

公开(公告)号：US06278308B1

公开(公告)日：2001-08-21

申请号：US09415760

申请日：1999-10-08

申请人： Hamid Partovi ,  Michael Golden ,  John Yong

发明人： Hamid Partovi ,  Michael Golden ,  John Yong

IPC分类号： H03K312

CPC分类号： H03K3/356139 ,  H03K3/012

摘要： A flip-flop circuit includes a differential stage coupled to a transparent latch. Respective sides of the differential stage, referred to as the “output side” and the “reference side,” are precharged high during a precharge phase. During an evaluation phase, the state of a data input signal is sensed. Depending upon the state of the data input signal, either the output side or the reference side is discharged. Also, during the evaluation phase, the transparent latch is enabled, and thereby samples and stores an output signal from the output side of the differential stage. Upon initiation of the next precharge phase, the transparent latch is quickly disabled (i.e., is placed in an opaque state), and retains its present state. Since only a single side of the differential stage is used to drive the transparent latch, the differential stage may advantageously be implemented in an asymmetric fashion. In yet an additional embodiment, complex logic may be added to the differential stage of the flip-flop circuit.

摘要翻译： 触发器电路包括耦合到透明锁存器的差分级。 被称为“输出侧”和“参考侧”的差分级的各个侧在预充电阶段被预充电为高电平。 在评估阶段，检测数据输入信号的状态。 根据数据输入信号的状态，输出侧或参考侧都被放电。 此外，在评估阶段期间，透明锁存器被使能，从而采样并存储来自差分级的输出侧的输出信号。 在下一个预充电阶段开始时，透明锁存器被快速禁用（即，处于不透明状态）并保持其当前状态。 由于仅使用差分级的单侧来驱动透明锁存器，差动级可有利地以非对称方式实现。 在又一个实施例中，复合逻辑可以被添加到触发器电路的差分级。

公开(公告)号：US5764089A

公开(公告)日：1998-06-09

申请号：US706212

申请日：1996-08-30

申请人： Hamid Partovi ,  Robert C. Burd ,  Udin Salim ,  Frederick Weber ,  Luigi Di Gregorio ,  Donald A. Draper

发明人： Hamid Partovi ,  Robert C. Burd ,  Udin Salim ,  Frederick Weber ,  Luigi Di Gregorio ,  Donald A. Draper

IPC分类号： H03K3/037 ,  H03K3/356

CPC分类号： H03K3/356121 ,  H03K3/037

摘要： A high-performance dynamic flip-flop circuit implementation. The dynamic flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (319). The flip-flop comprises a delay block (317) coupled to a clock input (305). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (440) of the delayed clock output (319) follows a rising edge (444) of a clock signal after a delay period (448). The flip-flop clocks in new data at a data input (305) in response to the clock input (310) during this delay period (448). Data is held in a storage block (360). The flip-flop has extremely good transient characteristics, especially set-up and clock-to-output times. The flip-flop consumes no static power.

摘要翻译： 高性能动态触发电路实现。 动态触发器电路包括“隐式”单触发以产生延迟时钟输出（319）。 触发器包括耦合到时钟输入（305）的延迟块（317）。 触发器可以是D型触发器。 在触发器的正边沿触发实施例中，延迟时钟输出（319）的下降沿（440）在延迟时段（448）之后的时钟信号的上升沿（444）之后。 触发器响应于在该延迟时段（448）期间的时钟输入（310）在数据输入（305）处的新数据中进行时钟。 数据保存在存储块（360）中。 触发器具有非常好的瞬态特性，特别是设置和时钟到输出时间。 触发器不消耗静电。

公开(公告)号：US5353424A

公开(公告)日：1994-10-04

申请号：US794865

申请日：1991-11-19

申请人： Hamid Partovi ,  William R. Wheeler ,  Michael Leary ,  Michael A. Case ,  Steven Butler ,  Rajesh Khanna

发明人： Hamid Partovi ,  William R. Wheeler ,  Michael Leary ,  Michael A. Case ,  Steven Butler ,  Rajesh Khanna

IPC分类号： G06F12/08

CPC分类号： G06F12/0895 ,  G06F12/0864

摘要： A tag comparator and bank selector for a set-associative cache in a computer system operates in a minimum time so that a cache hit or miss signal is generated early in a memory cycle. The data memory of the cache has two (or more) banks, with a tag store for each bank, and the two banks are accessed separately and in parallel using the index (low order address bits) while the tag translation is in progress. Two bit-by-bit tag compares are performed, one for each tag store, producing two multibit match indications, one bit for each tag bit in each tag store. These two match indications are applied to two separate dynamic NOR gates, and the two outputs applied to a logic circuit to detect a hit and generate a bank-select output. There are four possible outcomes from the compare operation: both banks miss, left bank hits, right bank hits, and both banks hit. The later condition indicates a possible ambiguity, and neither data item should be used, so a miss is signalled. The comparator is in large part self-timed using a flow-through design, as distinguished from being enabled on clock edges. Delay elements in the bank select logic allow the banks to be timed against each other, and current limiters are employed to equalize the timing of miss signals, regardless of the number of match lines switching high (which is data dependent). An address producing 19-of-20 match bits will result in a NOR gate output of about the same timing as an address producing no match bits, even though the former will turn on only one transistor to discharge the precharged output node of the NOR gate, whereas the later will turn on twenty paths for discharge. Although a two-way set associative cache is shown herein as an example embodiment, one of the features of the invention is that higher levels of associativity, e.g., four-way and eight-way, are equally well accommodated.

摘要翻译： 用于计算机系统中的组相关高速缓存的标签比较器和存储体选择器在最小时间内操作，使得在存储器周期中早期产生高速缓存命中或未命中信号。 高速缓存的数据存储器具有两个（或更多个）存储体，每个存储体具有标签存储，并且当标签转换正在进行时，使用索引（低位地址位）分开存取和并行访问两个存储体。 执行两个逐位标签比较，每个标签存储一个，产生两个多位匹配指示，每个标签存储中每个标签位一位。 这两个匹配指示被应用于两个单独的动态NOR门，并且两个输出被施加到逻辑电路以检测命中并产生一个存储体选择输出。 比较操作有四个可能的结果：两家银行错失，左岸点击，右岸点击，两家银行都受到打击。 后面的条件表示可能的模糊性，并且都不应该使用数据项，所以发出了错误信号。 使用流通设计，比较器在很大程度上是自定时的，与时钟边沿不同。 银行选择逻辑中的延迟元素允许银行彼此定时，并且采用电流限制器来均衡缺失信号的定时，而不管匹配线的数量如何切换高（这取决于数据）。 产生20位20位匹配位的地址将导致与不产生不匹配位的地址大致相同的定时的或非门输出，即使前者将仅接通一个晶体管来放电NOR门的预充电输出节点 ，而后来将打开二十条出路。 尽管本文中示出了双向组关联高速缓存作为示例实施例，但是本发明的特征之一是更高级别的关联性，例如四路和八路同样适应。

公开(公告)号：US5253203A

公开(公告)日：1993-10-12

申请号：US2689

申请日：1993-01-11

申请人： Hamid Partovi ,  Michael A. Case

发明人： Hamid Partovi ,  Michael A. Case

IPC分类号： G06F12/08 ,  G06F12/10 ,  G11C7/10 ,  G11C15/00 ,  G11C15/04 ,  G11C7/00

CPC分类号： G11C7/10 ,  G06F12/0893 ,  G06F12/1054

摘要： The physical organization of a memory cell array in an integrated circuit cache memory system is different from its logical organization because the bit lines of the array are divided into segments to physically divide the memory cell array into sub-arrays, and multiplexing the bit line segments of groups of neighboring bit lines are multiplexed to respective data lines. "Early" address bits control row decoders which select a row of memory cells in each sub-array to assert data signals on the bit line segments in each sub-array. "Late" address bits control the multiplexing of the data signals on the bit line segments to the data lines. By segmenting the bit lines, the number of "late" address bits is increased relative to the number of "early" address bits to increase the memory access speed in data processing systems that employ virtual addressing but store data in cache memory in association with physical addresses. The "late" address bits, for example, are a translated portion of a virtual address translated by a translation buffer, and the "early" address bits are an untranslated portion of the virtual address. Routing problems are avoided by extending the data lines in parallel with the bit lines over regions of the integrated circuit substrate allocated to the memory cells in the array, and forming the data lines in a metalization layer separate from and over a metalization layer of the bit lines. Each data line is multiplexed to multiple bit line segments to eliminate a final multiplexer to input/output lines.

摘要翻译： 集成电路高速缓冲存储器系统中的存储单元阵列的物理组织与其逻辑组织不同，因为阵列的位线被划分成段以物理地将存储单元阵列划分为子阵列，并且复用位线段 的相邻位线组被复用到相应的数据线。 “早期”地址位控制行解码器，其选择每个子阵列中的一行存储器单元以在每个子阵列中的位线段上断言数据信号。 “晚”地址位控制位线段上的数据信号到数据线的复用。 通过对位线进行分段，相对于“早期”地址位的数量“晚”地址位的数量增加，以增加采用虚拟寻址的数据处理系统中的存储器访问速度，而将数据与物理存储器相关联地存储在高速缓冲存储器中 地址 例如，“晚”地址位是由翻译缓冲器转换的虚拟地址的翻译部分，并且“早期”地址位是虚拟地址的未翻译部分。 通过在分配给阵列中的存储器单元的集成电路衬底的区域上与位线并行地延伸数据线来避免路由问题，并且在与位的金属化层分开的金属化层中形成数据线 线条。 每个数据线被复用到多个位线段以消除最后的多路复用器到输入/输出线。

公开(公告)号：US4857770A

公开(公告)日：1989-08-15

申请号：US161810

申请日：1988-02-29

申请人： Hamid Partovi ,  Michael A. Van Buskirk

发明人： Hamid Partovi ,  Michael A. Van Buskirk

IPC分类号： H03K17/04 ,  G11C7/10 ,  G11C11/409 ,  H03K17/16 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0185

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  H03K19/00361

摘要： An output buffer arrangement includes a first stable, controlled current source (MO1), a first bidirectional-switching device (24) including a CMOS transmission gate and being responsive to the first current source (MO1) for charging the gate of a pull-up transistor (MO5), a second stable, controlled current source (MO6), and a second bidirectional-switching device (27) including a second CMOS transmission gate and being responsive to the second current source (MO6) for charging the gate of a pull-down transistor (MO10). The output buffer arrangement reduces induced chip noise at low temperature, high power supply voltage without degrading substantially its high operational speed.