公开(公告)号：US20050235180A1

公开(公告)日：2005-10-20

申请号：US11090831

申请日：2005-03-24

申请人： Gerd Frankowsky

发明人： Gerd Frankowsky

IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R31/3193 ,  G06F3/00 ,  G11C29/00 ,  G11C29/26 ,  G11C29/44

CPC分类号： G11C29/1201 ,  G01R31/31723 ,  G01R31/3193 ,  G11C29/26 ,  G11C29/44 ,  G11C2029/2602

摘要： The invention relates to a module having a first integrated circuit and a second integrated circuit which are arranged on separate substrates, having a first output terminal and a second output terminal to which the first and second integrated circuits are respectfully connected in a parallel manner, and having a first selection terminal and a second selection terminal which are mutually separate and are connected to the first and second integrated circuits, respectively. A test circuit is provided in each of the integrated circuits to generate an error signal depending on whether an error occurred during a test operation, and an output circuit is provided in each of the integrated circuits to select the first output terminal or the second output terminal, depending on a selection signal that is applied to the respective selection terminal, for the purpose of outputting a state that indicates the error.

摘要翻译： 本发明涉及一种具有第一集成电路和第二集成电路的模块，该第一集成电路和第二集成电路布置在分离的基板上，具有第一输出端和第二输出端，第一和第二集成电路以平行的方式相互连接， 具有分别相互分离并连接到第一和第二集成电路的第一选择端子和第二选择端子。 在每个集成电路中提供测试电路，以根据在测试操作期间是否发生错误来生成误差信号，并且在每个集成电路中提供输出电路以选择第一输出端子或第二输出端子 取决于施加到各个选择终端的选择信号，以便输出指示错误的状态。

公开(公告)号：US20050046436A1

公开(公告)日：2005-03-03

申请号：US10894942

申请日：2004-07-20

申请人： Gerd Frankowsky ,  Thorsten Bucksch ,  Gerd Brosamlen

发明人： Gerd Frankowsky ,  Thorsten Bucksch ,  Gerd Brosamlen

IPC分类号： G01R31/319 ,  G01R31/26

CPC分类号： G01R31/3191 ,  G01R31/31905

摘要： One embodiment of the invention provides a calibration device for the calibration of a tester channel of a tester device to which integrated components on a substrate wafer can be contact-connected for testing with electrical signals. The calibration device includes a connecting device and a planar contact carrier with a first contact area and a second contact area insulated from the first contact area, which can be electrically connected via the connecting device, the connecting device being suitable for connecting the first and second contact areas to the tester device, the first contact area being generally surrounded by the second contact area, so that, when a needle card connected to the tester device is placed onto the contact carrier of the calibration device, one of the contact-connecting needles of the needle card which is connected to the tester channel to be calibrated is placed onto the first contact area and a plurality or all of the further contact-connecting needles of the needle card at tester channels that are not to be calibrated are placed onto the second contact area.

摘要翻译： 本发明的一个实施例提供了一种用于校准测试器设备的测试器通道的校准装置，衬底晶片上的集成部件可以与其接触连接以便用电信号进行测试。 校准装置包括连接装置和具有第一接触区域和与第一接触区域绝缘的第二接触区域的平面接触载体，所述第一接触区域可以经由连接装置电连接，所述连接装置适于连接第一和第二接触区域 所述第一接触区域通常被所述第二接触区域包围，使得当连接到所述测试器装置的针卡被放置在所述校准装置的接触载体上时，所述接触连接针 将连接到要校准的测试器通道的针卡放置在第一接触区域上，并且将未被校准的测试器通道处的针卡的多个或所有另外的接触连接针放置在 第二接触区域。

公开(公告)号：US06734474B2

公开(公告)日：2004-05-11

申请号：US10200933

申请日：2002-07-23

申请人： Gerd Frankowsky

发明人： Gerd Frankowsky

IPC分类号： H01L2710

CPC分类号： H01L25/0657 ,  H01L23/5252 ,  H01L23/5256 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： For a selection of semiconductor chips stacked on top of one another, the invention includes leading through selection contact points of one chip on a rear side thereof and connecting them to corresponding selection contact points of the other semiconductor chip. Programmable input amplifiers are programmed to be transmissive or blocking through fuses/antifuses so that selection signals applied to the selection contact points either activate or block functional elements only of one or only of the other semiconductor chip. As a result, simple stacking of identically prefabricated semiconductor chips is made possible.

摘要翻译： 对于堆叠在彼此之上的半导体芯片的选择，本发明包括通过其后侧的一个芯片的选择接触点，并将它们连接到另一个半导体芯片的对应选择接触点。 可编程输入放大器被编程为通过熔丝/反熔丝进行透射或阻挡，使得施加到选择接触点的选择信号仅激活或阻止仅一个或仅另一个半导体芯片的功能元件。 结果，可以简单地堆叠相同的预制半导体芯片。

公开(公告)号：US06714418B2

公开(公告)日：2004-03-30

申请号：US10285924

申请日：2002-11-01

申请人： Gerd Frankowsky ,  Harry Hedler ,  Roland Irsigler ,  Thorsten Meyer ,  Barbara Vasquez

发明人： Gerd Frankowsky ,  Harry Hedler ,  Roland Irsigler ,  Thorsten Meyer ,  Barbara Vasquez

IPC分类号： H05K702

CPC分类号： H01L25/50 ,  H01L21/568 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/15331 ,  H01L2924/00

摘要： An electronic component has a plurality of chips which are stacked one above the other and contact-connected to one another. To form this component, a first planar chip arrangement is provided with the functional chips spaced apart from one another in a grid and with a filling material in the spaces between the chips to form an insulating holding frame that fixes the chips, the frame has chip-dedicated contact-connecting elements that serve for the electrical contact-connection to another chip of another chip arrangement and each chip has dedicated electrically conductive strips. At least one additional planar chip arrangement is formed by the same method as the first planar chip arrangement and is then stacked on the first planar chip arrangement so that the two chip arrangements lie one above the other and the respective contact-connecting elements of the two chip arrangements are connected to one another for electrical chip-to-chip contact-connection. Subsequently, each of the components, which comprise a stack of chips, is separated from the assembled stack of chip arrangements.

摘要翻译： 电子部件具有多个彼此叠置并彼此接触连接的芯片。 为了形成该部件，第一平面芯片布置设置有功能芯片，其格栅彼此间隔开，并且在芯片之间的空间中具有填充材料，以形成固定芯片的绝缘保持框架，框架具有芯片 用于与另一个芯片布置的另一芯片的电接触连接的每个芯片具有专用的导电条。 通过与第一平面芯片布置相同的方法形成至少一个附加的平面芯片布置，然后将其堆叠在第一平面芯片布置上，使得两个芯片布置在另一个之上并且两个相应的触点连接元件 芯片布置彼此连接以进行电芯片到芯片的接触连接。 随后，包括一堆芯片的每个部件与组装的芯片布置堆叠分离。

公开(公告)号：US06696319B2

公开(公告)日：2004-02-24

申请号：US10244256

申请日：2002-09-16

申请人： Gerd Frankowsky ,  Thorsten Meyer

发明人： Gerd Frankowsky ,  Thorsten Meyer

IPC分类号： H01L2144

CPC分类号： H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/17517 ,  H01L2224/45144 ,  H01L2224/81136 ,  H01L2224/81801 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/00

摘要： A method of attaching semiconductor devices, the contact devices of which have preferably already been applied at wafer level, on a switching device and such a device includes having the electrical contacts remain free of solder by using flexible contact elements, and performing the mechanical attachment by additional attachment elements or compression stops used as attachment elements.

摘要翻译： 将其接触装置优选地已经以晶片级施加在其上的半导体器件的方法在开关器件上，并且这种器件包括通过使用柔性接触元件使电触头保持不含焊料，并且通过使用柔性接触元件执行机械附接 用作附件的附加附件或压缩挡块。

公开(公告)号：US06677770B2

公开(公告)日：2004-01-13

申请号：US09906886

申请日：2001-07-17

申请人： Gerd Frankowsky

发明人： Gerd Frankowsky

IPC分类号： G01R31102

CPC分类号： G01R1/0483

摘要： A test socket for a semiconductor device includes a guide plate operable to receive the semiconductor device and to maintain electrical terminals of the semiconductor device in registration with electrical terminals of a base, a shell operable to couple to the base and to maintain the guide plate in registration with the electrical terminals of the base, the shell including an aperture in communication with the base through which the guide plate can be inserted and removed when the shell is coupled to the base; and at least one fastener coupled to the shell and operable to maintain the semiconductor device in engagement with the guide plate and to urge the electrical terminals of the semiconductor device in contact with the electrical terminals of the base. A method for operating the test socket is also disclosed.

摘要翻译： 用于半导体器件的测试插座包括可操作以接收半导体器件并且将半导体器件的电端子保持与基座的电端子对准的引导板，可操作以耦合到基座并将引导板保持在 与底座的电气端子对准，壳体包括与底座连通的孔，当壳体联接到基座时，引导板可以通过该孔插入和移除; 以及至少一个紧固件，其联接到壳体并且可操作以保持半导体器件与引导板接合并且促使半导体器件的电端子与基座的电端子接触。 还公开了一种用于操作测试插座的方法。

公开(公告)号：US06367027B1

公开(公告)日：2002-04-02

申请号：US09273842

申请日：1999-03-22

申请人： Gerd Frankowsky

发明人： Gerd Frankowsky

IPC分类号： G06F1300

CPC分类号： G06F5/06

摘要： A pointer generation circuit, in accordance with the invention, includes a clock for providing a clock cycle, and a shift register with a plurality of latches for storing data bits. A first latch receives a flag bit upon a first clock cycle of the clock. A switch transfers the flag bit to the shift register on the first clock cycle. The switch connects a last latch to the first latch after the flag bit is transferred to the shift register. The flag bit is transferred to a next latch, wherein the next latch for the last latch is the first latch, at each consecutive clock cycle thereby generating pointer signals in accordance with the clock cycle and the data bits stored in the latches.

摘要翻译： 根据本发明的指针生成电路包括用于提供时钟周期的时钟和具有用于存储数据位的多个锁存器的移位寄存器。 第一个锁存器在时钟的第一个时钟周期接收一个标志位。 开关在第一个时钟周期将标志位传送到移位寄存器。 标志位转移到移位寄存器后，开关将最后一个锁存器连接到第一个锁存器。 标志位被传送到下一个锁存器，其中在每个连续的时钟周期，用于最后一个锁存器的下一个锁存器是第一个锁存器，从而根据存储在锁存器中的时钟周期和数据位产生指针信号。

公开(公告)号：US07483326B2

公开(公告)日：2009-01-27

申请号：US10374916

申请日：2003-02-26

申请人： Gerd Frankowsky

发明人： Gerd Frankowsky

IPC分类号： G11C17/18

CPC分类号： G11C17/18 ,  G11C17/16 ,  G11C29/027

摘要： The present invention provides an apparatus for monitoring a state, in particular of a fuse (4), having: a first state storage device (11) for storing a state, in particular of a fuse (4); a second state storage device (12) for storing the state of the first state storage device (11); and a logic device (9) for comparing the states of the two state stores (11, 12); the first state store (11) being able to be driven for renewed reading in of the state, in particular of the fuse (4), in the event of a noncorrespondence of the states in the two stores (11, 12). The present invention likewise provides a method for monitoring a state, in particular of a fuse.

摘要翻译： 本发明提供了一种用于监视特别是保险丝（4）的状态的装置，具有：用于存储特别是保险丝（4）的状态的第一状态存储装置（11）。 用于存储第一状态存储装置（11）的状态的第二状态存储装置（12）。 以及用于比较两个状态存储器（11,12）的状态的逻辑设备（9）。 在两个商店（11,12）中的状态不相关的情况下，第一状态商店（11）能够被驱动以更新该状态，特别是保险丝（4）的读取。 本发明同样提供了一种用于监视特别是保险丝的状态的方法。

公开(公告)号：US07228473B2

公开(公告)日：2007-06-05

申请号：US11090831

申请日：2005-03-24

申请人： Gerd Frankowsky

发明人： Gerd Frankowsky

IPC分类号： G01R31/28

CPC分类号： G11C29/1201 ,  G01R31/31723 ,  G01R31/3193 ,  G11C29/26 ,  G11C29/44 ,  G11C2029/2602

摘要： The invention relates to a module having a first integrated circuit and a second integrated circuit which are arranged on separate substrates, having a first output terminal and a second output terminal to which the first and second integrated circuits are respectfully connected in a parallel manner, and having a first selection terminal and a second selection terminal which are mutually separate and are connected to the first and second integrated circuits, respectively. A test circuit is provided in each of the integrated circuits to generate an error signal depending on whether an error occurred during a test operation, and an output circuit is provided in each of the integrated circuits to select the first output terminal or the second output terminal, depending on a selection signal that is applied to the respective selection terminal, for the purpose of outputting a state that indicates the error.

摘要翻译： 本发明涉及一种具有第一集成电路和第二集成电路的模块，该第一集成电路和第二集成电路布置在分离的基板上，具有第一输出端和第二输出端，第一和第二集成电路以平行的方式相互连接， 具有分别相互分离并连接到第一和第二集成电路的第一选择端子和第二选择端子。 在每个集成电路中提供测试电路，以根据在测试操作期间是否发生错误来生成误差信号，并且在每个集成电路中提供输出电路以选择第一输出端子或第二输出端子 取决于施加到各个选择终端的选择信号，以便输出指示错误的状态。

公开(公告)号：US07208968B2

公开(公告)日：2007-04-24

申请号：US10865050

申请日：2004-06-10

申请人： Frank Weber ,  Gerd Frankowsky

发明人： Frank Weber ,  Gerd Frankowsky

IPC分类号： G01R31/26

CPC分类号： G01R31/2863 ,  G01R31/2889

摘要： Test system for testing integrated chips and an adapter element for a test system. One embodiment provides a test system for testing integrated chips in a burn-in test operation, the integrated chips to be tested being arranged in groups on a burn-in board, the burn-in board having a first connecting device in order to connect the burn-in board to a tester device, the tester device comprising a test module with a test circuit in order to test chips on the burn-in board in accordance with the burn-in test operation, the test module having a second connecting device in order to connect the burn-in board to the test module via the second connecting device, a plurality of test modules being provided, the second connecting devices of which can be contact-connected to a plurality of third connecting devices of an adapter element, the adapter element having a fourth connecting device for contact-connection of the first connecting device of the burn-in board, the third connecting devices of the adapter element being connected to the fourth connecting device in such a way that, in the contact-connected state, it is possible to test each integrated circuit of a group with one of the test modules.

摘要翻译： 用于测试集成芯片的测试系统和用于测试系统的适配器元件。 一个实施例提供了一种用于在老化测试操作中测试集成芯片的测试系统，待测试的集成芯片分组放置在老化板上，该老化板具有第一连接设备，以便连接 所述测试装置包括具有测试电路的测试模块，以便根据所述老化测试操作在所述老化板上测试芯片，所述测试模块具有第二连接装置， 为了通过第二连接装置将老化板连接到测试模块，提供了多个测试模块，其中第二连接装置可以与适配器元件的多个第三连接装置接触连接， 适配器元件具有用于接合连接老化板的第一连接装置的第四连接装置，适配器元件的第三连接装置以这样的方式连接到第四连接装置 在接触连接状态下，可以用一个测试模块来测试组中的每个集成电路。