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220 条记录 (耗时 0.036 秒)

    Semiconductor memory device
    41.
    发明授权
    Semiconductor memory device 失效

    公开(公告)号：US5943284A

    公开(公告)日：1999-08-24

    申请号：US705315

    申请日：1996-08-29

    申请人： Hiroyuki Mizuno ,  Suguru Tachibana ,  Koichiro Ishibashi ,  Kenichi Osada

    发明人： Hiroyuki Mizuno ,  Suguru Tachibana ,  Koichiro Ishibashi ,  Kenichi Osada

    IPC分类号： G11C11/41 ,  G06F12/08 ,  G11C5/06 ,  G11C7/06 ,  G11C7/18 ,  G11C7/22 ,  G11C11/401 ,  G11C11/409 ,  G11C13/00

    CPC分类号： G11C7/18 ,  G06F12/0893 ,  G11C5/063 ,  G11C7/06 ,  G11C7/22 ,  G11C2207/108 ,  Y02B60/1225

    摘要： A memory structure/circuit has at least two memory cell arrays connected to each other in a hierarchy. The bit lines of the two or more memory cell arrays are connected by hierarchy switches. The memory cells of one of the arrays can be read out faster than the others by using the hierarchy switches to select one array without selecting the other arrays. So the data that is read with higher frequency can be selectively read out faster if it is stored in the faster access memory array. If the data in the faster access memory cell array includes a copy of the data in the other array, it can be used as a cache memory. A tag array and data array in combination that are connected to another tag array and data array in combination through hierarchy switch connections can provide a cache memory that is direct mapped or set associative, and also full associative. The memory device can be used in a semiconductor data processor having a CPU in which the memory device is connected to the CPU through a bus, wherein both the CPU and the memory device are formed on a single semiconductor substrate. The memory device can also be an off-chip device.

    Substrate bias switching unit for a low power processor
    42.
    发明授权
    Substrate bias switching unit for a low power processor 失效
    用于低功耗处理器的基板偏置开关单元

    公开(公告)号：US07958379B2

    公开(公告)日：2011-06-07

    申请号：US12346268

    申请日：2008-12-30

    申请人： Yonetaro Totsuka ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

    发明人： Yonetaro Totsuka ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

    IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F1/32 ,  B23K11/24

    CPC分类号： G06F1/3296 ,  G06F1/3203 ,  Y02D10/172 ,  Y02D50/20

    摘要： The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.

    摘要翻译： 本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压 待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放 在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。

    Semiconductor integrated circuit
    43.
    发明申请
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US20080136502A1

    公开(公告)日：2008-06-12

    申请号：US11987073

    申请日：2007-11-27

    申请人： Hiroyuki Mizuno ,  Koichiro Ishibashi ,  Takanori Shimura ,  Toshihiro Hattori

    发明人： Hiroyuki Mizuno ,  Koichiro Ishibashi ,  Takanori Shimura ,  Toshihiro Hattori

    IPC分类号： G05F3/16 ,  G05F3/02

    CPC分类号： H01L27/0207 ,  G11C5/14 ,  G11C5/146 ,  G11C5/147 ,  H01L27/0928 ,  H01L27/11807 ,  H01L2924/0002 ,  H03K19/0016 ,  H01L2924/00

    摘要： In order to provide a semiconductor IC unit such as a microprocessor, etc., which satisfies both fast operation and lower power consumption properties with its high quality kept, the semiconductor IC unit of the present invention is composed so as to include a main circuit (LOG) provided with transistors, which is formed on a semiconductor substrate, and a substrate bias controlling circuit (VBC) used for controlling a voltage to be applied to the substrate, and the main circuit includes switching transistors (MN1 and MP1) used for controlling a voltage to be applied to the substrate and control signals output from the substrate bias controlling circuit is entered to the gate of each of the switching transistors and the control signal is returned to the substrate bias controlling circuit.

    摘要翻译： 为了提供满足快速操作和低功耗特性的诸如微处理器等的半导体IC单元，保持其高质量，本发明的半导体IC单元被构成为包括主电路（ LOG），其形成在半导体衬底上的晶体管和用于控制施加到衬底的电压的衬底偏置控制电路（VBC），并且主电路包括使用的开关晶体管（MN 1和MP 1） 用于控制施加到衬底的电压，并且从衬底偏置控制电路输出的控制信号被输入到每个开关晶体管的栅极，并且控制信号返回到衬底偏置控制电路。

    Semiconductor device including a prediction circuit to control a power status control circuit which controls the power status of a function circuit
    45.
    发明授权
    Semiconductor device including a prediction circuit to control a power status control circuit which controls the power status of a function circuit 有权
    半导体器件包括用于控制功率状态控制电路的预测电路，其控制功能电路的电源状态

    公开(公告)号：US07222244B2

    公开(公告)日：2007-05-22

    申请号：US09932099

    申请日：2001-08-20

    申请人： Takayuki Kawahara ,  Takehiro Shimizu ,  Fumio Arakawa ,  Hiroyuki Mizuno ,  Takao Watanabe ,  Koichiro Ishibashi

    发明人： Takayuki Kawahara ,  Takehiro Shimizu ,  Fumio Arakawa ,  Hiroyuki Mizuno ,  Takao Watanabe ,  Koichiro Ishibashi

    IPC分类号： G06F1/32

    CPC分类号： H03K19/0016 ,  H03K19/1735

    摘要： A semiconductor device having a functional circuit block with predictive power controller is provided so as to construct a system LSI manufactured in a practicable number of design steps, which is extensible and in which power is reduced. The functional circuit block includes a prediction circuit and a predictive power shutdown circuit having a power status control circuit. The prediction circuit controls a power status of the functional circuit block by using the power status control circuit, based on input information thereto. When no information is inputted for a predetermined a period of time, the power status control circuit shifts from a power status of the functional circuit block to a low-power status.

    摘要翻译： 提供具有预测功率控制器的具有功能电路块的半导体器件，以便构建以可实施的数量的设计步骤制造的系统LSI，其是可扩展的并且功率减小。 功能电路块包括具有电源状态控制电路的预测电路和预测功率关断电路。 预测电路根据其输入信息，通过使用电源状态控制电路来控制功能电路块的电源状态。 当在预定的一段时间内没有输入信息时，电源状态控制电路从功能电路块的电源状态转换为低功率状态。

    Semiconductor integrated circuit
    48.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US06707334B2

    公开(公告)日：2004-03-16

    申请号：US10443018

    申请日：2003-05-22

    申请人： Hiroyuki Mizuno ,  Koichiro Ishibashi ,  Takanori Shimura ,  Toshihiro Hattori

    发明人： Hiroyuki Mizuno ,  Koichiro Ishibashi ,  Takanori Shimura ,  Toshihiro Hattori

    IPC分类号： H03K301

    CPC分类号： H01L27/0207 ,  G11C5/14 ,  G11C5/146 ,  G11C5/147 ,  H01L27/0928 ,  H01L27/11807 ,  H01L2924/0002 ,  H03K19/0016 ,  H01L2924/00

    摘要： In order to provide a semiconductor IC unit such as a microprocessor, etc., which satisfies both fast operation and lower power consumption properties with its high quality kept, the semiconductor IC unit of the present invention is composed so as to include a main circuit (LOG) provided with transistors, which is formed on a semiconductor substrate, and a substrate bias controlling circuit (VBC) used for controlling a voltage to be applied to the substrate, and the main circuit includes switching transistors (MN1 and MP1) used for controlling a voltage to be applied to the substrate and control signals output from the substrate bias controlling circuit is entered to the gate of each of the switching transistors and the control signal is returned to the substrate bias controlling circuit.

    摘要翻译： 为了提供满足快速操作和低功耗特性的诸如微处理器等的半导体IC单元，保持其高质量，本发明的半导体IC单元被构成为包括主电路（ LOG），其形成在半导体衬底上的晶体管和用于控制施加到衬底的电压的衬底偏置控制电路（VBC），并且主电路包括用于控制的开关晶体管（MN1和MP1） 将要施加到衬底的电压和从衬底偏置控制电路输出的控制信号输入到每个开关晶体管的栅极，并且控制信号返回到衬底偏置控制电路。