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    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US06353569B1

    公开(公告)日：2002-03-05

    申请号：US09291272

    申请日：1999-04-14

    申请人： Hiroyuki Mizuno ,  Suguru Tachibana ,  Koichiro Ishibashi ,  Kenichi Osada

    发明人： Hiroyuki Mizuno ,  Suguru Tachibana ,  Koichiro Ishibashi ,  Kenichi Osada

    IPC分类号： G11C1300

    CPC分类号： G11C7/18 ,  G06F12/0893 ,  G11C5/063 ,  G11C7/06 ,  G11C7/22 ,  G11C2207/108 ,  Y02D10/13

    摘要： A memory structure/circuit has at least two memory cell arrays connected to each other in a hierarchy. The bit lines of the two or more memory cell arrays are connected by hierarchy switches. The memory cells of one of the arrays can be read out faster than the others by using the hierarchy switches to select one array without selecting the other arrays. So the data that is read with higher frequency can be selectively read out faster if it is stored in the faster access memory array. If the data in the faster access memory cell array includes a copy of the data in the other array, it can be used as a cache memory. A tag array and data array in combination that are connected to another tag array and data array in combination through hierarchy switch connections can provide a cache memory that is direct mapped or set associative, and also full associative. The memory device can be used in a semiconductor data processor having a CPU in which the memory device is connected to the CPU through a bus, wherein both the CPU and the memory device are formed on a single semiconductor substrate. The memory device can also be an off-chip device.

    摘要翻译： 存储器结构/电路具有至少两个相互连接的存储单元阵列。 两个或多个存储单元阵列的位线通过分层开关连接。 通过使用层次结构开关选择一个阵列而不选择其他阵列，其中一个阵列的存储单元可以比其他阵列更快地读出。 因此，如果存储在更快的访问存储器阵列中，则可以更快地选择性地读出更高频率读取的数据。 如果快速访问存储单元阵列中的数据包含另一阵列中的数据副本，则可以将其用作高速缓冲存储器。 组合的标签阵列和数据阵列通过分层交换机连接组合连接到另一标签阵列和数据阵列，可以提供直接映射或设置关联的高速缓存存储器，也可以是完全关联的。 存储器件可用于具有CPU的半导体数据处理器，其中存储器件通过总线连接到CPU，其中CPU和存储器件均形成在单个半导体衬底上。 存储器件也可以是片外器件。

    Semiconductor memory device
    2.
    发明授权
    Semiconductor memory device 失效

    公开(公告)号：US06525985B2

    公开(公告)日：2003-02-25

    申请号：US09577366

    申请日：2000-05-23

    申请人： Hiroyuki Mizuno ,  Suguru Tachibana ,  Koichiro Ishibashi ,  Kenichi Osada

    发明人： Hiroyuki Mizuno ,  Suguru Tachibana ,  Koichiro Ishibashi ,  Kenichi Osada

    IPC分类号： G11C514

    CPC分类号： G11C7/18 ,  G06F12/0893 ,  G11C5/063 ,  G11C7/06 ,  G11C7/22 ,  G11C2207/108 ,  Y02D10/13

    摘要： A memory structure/circuit has at least two memory cell arrays connected to each other in a hierarchy. The bit lines of the two or more memory cell arrays are connected by hierarchy switches. The memory cells of one of the arrays can be read out faster than the others by using the hierarchy switches to select one array without selecting the other arrays. So the data that is read with higher frequency can be selectively read out faster if it is stored in the faster access memory array. If the data in the faster access memory cell array includes a copy of the data in the other array, it can be used as a cache memory. A tag array and data array in combination that are connected to another tag array and data array in combination through hierarchy switch connections can provide a cache memory that is direct mapped or set associative, and also full associative. The memory device can be used in a semiconductor data processor having a CPU in which the memory device is connected to the CPU through a bus, wherein both the CPU and the memory device are formed on a single semiconductor substrate. The memory device can also be an off-chip device.

    Semiconductor memory device
    3.
    发明授权
    Semiconductor memory device 失效

    公开(公告)号：US5943284A

    公开(公告)日：1999-08-24

    申请号：US705315

    申请日：1996-08-29

    申请人： Hiroyuki Mizuno ,  Suguru Tachibana ,  Koichiro Ishibashi ,  Kenichi Osada

    发明人： Hiroyuki Mizuno ,  Suguru Tachibana ,  Koichiro Ishibashi ,  Kenichi Osada

    IPC分类号： G11C11/41 ,  G06F12/08 ,  G11C5/06 ,  G11C7/06 ,  G11C7/18 ,  G11C7/22 ,  G11C11/401 ,  G11C11/409 ,  G11C13/00

    CPC分类号： G11C7/18 ,  G06F12/0893 ,  G11C5/063 ,  G11C7/06 ,  G11C7/22 ,  G11C2207/108 ,  Y02B60/1225

    摘要： A memory structure/circuit has at least two memory cell arrays connected to each other in a hierarchy. The bit lines of the two or more memory cell arrays are connected by hierarchy switches. The memory cells of one of the arrays can be read out faster than the others by using the hierarchy switches to select one array without selecting the other arrays. So the data that is read with higher frequency can be selectively read out faster if it is stored in the faster access memory array. If the data in the faster access memory cell array includes a copy of the data in the other array, it can be used as a cache memory. A tag array and data array in combination that are connected to another tag array and data array in combination through hierarchy switch connections can provide a cache memory that is direct mapped or set associative, and also full associative. The memory device can be used in a semiconductor data processor having a CPU in which the memory device is connected to the CPU through a bus, wherein both the CPU and the memory device are formed on a single semiconductor substrate. The memory device can also be an off-chip device.

    Semiconductor memory device
    4.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US06940739B2

    公开(公告)日：2005-09-06

    申请号：US10307954

    申请日：2002-12-03

    申请人： Hiroyuki Mizuno ,  Suguru Tachibana ,  Koichiro Ishibashi ,  Kenichi Osada

    发明人： Hiroyuki Mizuno ,  Suguru Tachibana ,  Koichiro Ishibashi ,  Kenichi Osada

    IPC分类号： G11C11/41 ,  G06F12/08 ,  G11C5/06 ,  G11C7/06 ,  G11C7/18 ,  G11C7/22 ,  G11C11/401 ,  G11C11/409

    CPC分类号： G11C7/18 ,  G06F12/0893 ,  G11C5/063 ,  G11C7/06 ,  G11C7/22 ,  G11C2207/108 ,  Y02D10/13

    摘要： A memory structure/circuit has at least two memory cell arrays connected to each other in a hierarchy. The bit lines of the two or more memory cell arrays are connected by hierarchy switches. The memory cells of one of the arrays can be read out faster than the others by using the hierarchy switches to select one array without selecting the other arrays. So the data that is read with higher frequency can be selectively read out faster if it is stored in the faster access memory array. If the data in the faster access memory cell array includes a copy of the data in the other array, it can be used as a cache memory. A tag array and data array in combination that are connected to another tag array and data array in combination through hierarchy switch connections can provide a cache memory that is direct mapped or set associative, and also full associative. The memory device can be used in a semiconductor data processor having a CPU in which the memory device is connected to the CPU through a bus, wherein both the CPU and the memory device are formed on a single semiconductor substrate. The memory device can also be an off-chip device.

    摘要翻译： 存储器结构/电路具有至少两个相互连接的存储单元阵列。 两个或多个存储单元阵列的位线通过分层开关连接。 通过使用层次结构开关选择一个阵列而不选择其他阵列，其中一个阵列的存储单元可以比其他阵列更快地读出。 因此，如果存储在更快的访问存储器阵列中，则可以更快地选择性地读出更高频率读取的数据。 如果快速访问存储单元阵列中的数据包含另一阵列中的数据副本，则可以将其用作高速缓冲存储器。 组合的标签阵列和数据阵列通过分层交换机连接组合连接到另一标签阵列和数据阵列，可以提供直接映射或设置关联的高速缓存存储器，也可以是完全关联的。 存储器件可用于具有CPU的半导体数据处理器，其中存储器件通过总线连接到CPU，其中CPU和存储器件均形成在单个半导体衬底上。 存储器件也可以是片外器件。

    Semiconductor integrated circuit device including SRAM memory cells having two P-channel MOS transistors and four N-channel MOS transistors and with four wiring layers serving as their gate electrodes
    6.
    发明授权
    Semiconductor integrated circuit device including SRAM memory cells having two P-channel MOS transistors and four N-channel MOS transistors and with four wiring layers serving as their gate electrodes 有权
    半导体集成电路器件包括具有两个P沟道MOS晶体管和四个N沟道MOS晶体管以及四个布线层作为其栅电极的SRAM存储单元

    公开(公告)号：US08482083B2

    公开(公告)日：2013-07-09

    申请号：US12821329

    申请日：2010-06-23

    申请人： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    发明人： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    IPC分类号： H01L29/76 ,  H01L27/11

    CPC分类号： H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/11 ,  H01L29/4916 ,  H01L29/783 ,  Y10S257/904

    摘要： Prior known static random access memory (SRAM) cells required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supply power to the substrate are formed in parallel to word lines in such a manner that one region is provided per group of thirty two memory cell rows or sixty four cell rows.

    摘要翻译： 现有已知的静态随机存取存储器（SRAM）单元需要将扩散层弯曲成键状形状，以便与其中形成有P型阱区的衬底电接触，这将导致不对称性的降低 导致出现微图案化困难的问题。 为了避免这个问题，构成SRAM单元的逆变器的P型阱区被细分成两部分，它们设置在N型阱区NW1的相对侧上，并形成为扩散 形成晶体管的层没有曲率，同时使得布局方向在平行于阱边界线和位线的方向上运行。 在阵列的中间位置处，用于向衬底供电的区域形成为平行于字线，以这样的方式，每组三十二个存储单元行或六十六个单元行提供一个区域。

    Semiconductor integrated circuit device
    7.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US07781846B2

    公开(公告)日：2010-08-24

    申请号：US12348524

    申请日：2009-01-05

    申请人： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    发明人： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    IPC分类号： H01L29/76 ,  H01L27/11

    CPC分类号： H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/11 ,  H01L29/4916 ,  H01L29/783 ,  Y10S257/904

    摘要： Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

    摘要翻译： 现有的已知的静态随机存取存储器（SRAM）单元需要将扩散层弯曲成键状形状，以便与其中形成有P型阱区的衬底进行电接触，这将导致 不对称性导致了微图案化困难的问题的发生。 为了避免这个问题，构成SRAM单元的逆变器的P型阱区被细分成两部分，它们设置在N型阱区NW1的相对侧上，并形成为扩散 形成晶体管的层没有曲率，同时使得布局方向在平行于阱边界线和位线的方向上运行。 在阵列的中间位置处，以与字线平行的方式形成用于向基板供电的区域，以每组三十二个存储单元行或六十四个单元行提供一个区域。