公开(公告)号：US06928540B2

公开(公告)日：2005-08-09

申请号：US09974559

申请日：2001-10-09

申请人： Nai-Shung Chang

发明人： Nai-Shung Chang

IPC分类号： G06F1/04 ,  G06F1/08 ,  G06F1/12 ,  G06F9/00

CPC分类号： G06F1/08

摘要： A system and a method capable of automatically reading out the multiple value of clock frequency on system bus are provided. The system includes a central processing unit and a chipset. The central processing unit has a storage unit for holding a multiple value of clock frequency. The storage unit is capable of synchronizing with an external device through a serial initialization packet (SIP) protocol. The chipset attempts to synchronize with the central processing unit in a SIP protocol that uses a preset multiple value of clock frequency as a parameter. If synchronization between the central processing unit and the chipset cannot be established, the preset multiple value of clock frequency is changed and the SIP protocol is executed again. The multiple value of clock frequency is reset until synchronization is established. After synchronization, the multiple value of clock frequency in the central processing unit is retrieved and compared with the preset multiple value of clock frequency. If the retrieved multiple value of clock frequency is different from the preset value in the chipset, the preset value is replaced by the retrieved value.

摘要翻译： 提供了能够在系统总线上自动读出时钟频率的多个值的系统和方法。 该系统包括中央处理单元和芯片组。 中央处理单元具有用于保持多个时钟频率值的存储单元。 存储单元能够通过串行初始化分组（SIP）协议与外部设备同步。 芯片组尝试以SIP协议与中央处理单元同步，SIP协议使用预设的多个时钟频率值作为参数。 如果中央处理单元与芯片组之间的同步不能建立，则改变预设的时钟频率倍数，再次执行SIP协议。 复位时钟频率的多个值，直到建立同步。 同步后，检索中央处理单元中的时钟频率的多个值，并将其与预设的时钟频率倍数进行比较。 如果检索到的时钟频率的多个值与芯片组中的预设值不同，则将预置值替换为检索到的值。

公开(公告)号：US06877102B2

公开(公告)日：2005-04-05

申请号：US10013983

申请日：2001-12-10

申请人： Nai-Shung Chang ,  Tsai-Sheng Chen ,  Shu-Hui Chen

发明人： Nai-Shung Chang ,  Tsai-Sheng Chen ,  Shu-Hui Chen

IPC分类号： G06F13/40 ,  G06F1/04

CPC分类号： G06F13/4068

摘要： A chipset to support multiple CPU's and a layout method thereof. Those independent signal lines for delivering high frequency clock signals of the chipset are isolated from using by other signals without being multiplexed. Trace length of the independent signal line is shorter than that of the others. The spaces between the independent signal line and others are also larger than that between other signal lines. Signal transmission quality is significantly upgraded because the high frequency clock signal is not multiplexed and isolated from others.

摘要翻译： 支持多CPU的芯片组及其布局方法。 用于传送芯片组的高频时钟信号的这些独立信号线与其他信号的使用隔离而不被复用。 独立信号线的跟踪长度短于其他信号线。 独立信号线与其他信号线之间的空间也大于其他信号线之间的间隔。 信号传输质量显着升高，因为高频时钟信号不被复用并与其隔离。

公开(公告)号：US20050017980A1

公开(公告)日：2005-01-27

申请号：US10710095

申请日：2004-06-18

申请人： Nai-Shung Chang ,  Chia-Hsing Yu ,  Lin Yang

发明人： Nai-Shung Chang ,  Chia-Hsing Yu ,  Lin Yang

IPC分类号： G06F3/14 ,  G06F13/14 ,  G06F13/36

CPC分类号： G06F3/14

摘要： The graphics display architecture provided by the present invention comprises an AGP slot, a PCIE slot, and a control chip set. The control chip set comprises a plurality of multi-defined pins, which are electrically coupled to the first pins of the AGP slot and the second pins of the PCIE slot simultaneously. When the first graphics adapter is plugged in the AGP slot and the first graphics adapter complies with AGP interface specification, the multi-defined pins serve to send/receive the signal complied with AGP interface specification. When the first graphics adapter is plugged in the AGP slot and the first graphics adapter complies with the Gfx interface, the multi-defined pins serve to send/receive the signal complied with the Gfx interface. When the second graphics adapter is plugged in the PCIE slot, the multi-defined pins serve to send/receive the signal complied wit the PCIE interface specification.

摘要翻译： 本发明提供的图形显示架构包括AGP槽，PCIE槽和控制芯片组。 控制芯片组包括多个多限定的引脚，它们同时电耦合到AGP插槽的第一引脚和PCIE插槽的第二引脚。 当第一个图形适配器插入AGP插槽并且第一个图形适配器符合AGP接口规范时，多重定义的引脚用于发送/接收符合AGP接口规范的信号。 当第一个图形适配器插入AGP插槽并且第一个图形适配器符合Gfx接口时，多重定义的引脚用于发送/接收符合Gfx接口的信号。 当第二个图形适配器插入PCIE插槽时，多重定义的引脚用于发送/接收符合PCIE接口规范的信号。

公开(公告)号：US06826635B2

公开(公告)日：2004-11-30

申请号：US09948871

申请日：2001-09-07

申请人： Nai-Shung Chang

发明人： Nai-Shung Chang

IPC分类号： G06F300

CPC分类号： G06F13/4072

摘要： An I/O pad has a data transmitting circuit, a data monitoring control circuit, and a control selection circuit. The control selection circuit controls the data transmitting circuit at the control end, so as to enable or disable the transmission. When it is enabled, data in the data transmitting circuit are exported to a receiving circuit. When it is disabled, data exportation stops. The data monitoring circuit receives signals of the data transmission circuit and export signals to the control selection circuit. The data monitoring circuit judges whether the data transmission is under a stable condition. If it is not yet, an unstable signal is exported to a first input end of the control selection circuit. A second input end of the control selection circuit receives an output enabling signal. The output end of the control selection circuit is connected to the control end of the data transmitting circuit. When the data transmission is at stable status and the output enabling signal indicates a disable status, the control selection circuit disables the data transmitting circuit. Otherwise, the control selection circuit enables the data transmitting circuit.

摘要翻译： I / O焊盘具有数据发送电路，数据监视控制电路和控制选择电路。 控制选择电路控制控制端的数据发送电路，以使能或禁止发送。 当使能时，数据发送电路中的数据被输出到接收电路。 禁用数据后，数据导出停止。 数据监视电路接收数据传输电路的信号并将信号输出到控制选择电路。 数据监视电路判断数据传输是否处于稳定状态。 如果还没有，则将不稳定的信号输出到控制选择电路的第一输入端。 控制选择电路的第二输入端接收输出使能信号。 控制选择电路的输出端连接到数据发送电路的控制端。 当数据传输处于稳定状态并且输出使能信号指示禁止状态时，控制选择电路禁止数据发送电路。 否则，控制选择电路使能数据发送电路。

公开(公告)号：US06813157B2

公开(公告)日：2004-11-02

申请号：US10156986

申请日：2002-05-28

申请人： Nai-Shung Chang

发明人： Nai-Shung Chang

IPC分类号： H05K700

CPC分类号： G11C5/04

摘要： A mother board and a computer system capable of flexibly using the SDRAM and the DDRAM. The mother board has several memory module slots, a voltage comparator, a clock generator and a chip set. Each of the memory module slots comprises a reference voltage pin, and the reference voltage pins of the memory module slots are connected to each other in parallel. The voltage comparator is coupled to the reference voltage pins of the memory module slots to detect whether the voltage at the reference voltage pin is equivalent to a reference voltage. The clock generator is coupled to an output of the voltage comparator. When the voltage at the reference voltage pin is equal to the reference voltage, a differential clock signal is generated, and when the votlage is different from the reference voltage, a normal clock signal is generated. The chip set is coupled to the output of the voltage comparator. When the voltage is equal to the reference voltage, the chip set is operated under a double data rate mode. If the voltage is different from the reference voltage, the chip set is operated under a normal data rate mode.

摘要翻译： 主板和能够灵活使用SDRAM和DDRAM的计算机系统。 母板具有多个存储器模块插槽，电压比较器，时钟发生器和芯片组。 每个存储器模块插槽包括参考电压引脚，并且存储器模块插槽的参考电压引脚彼此并联连接。 电压比较器耦合到存储器模块插槽的参考电压引脚，以检测参考电压引脚上的电压是否等于参考电压。 时钟发生器耦合到电压比较器的输出。 当参考电压引脚上的电压等于参考电压时，产生差分时钟信号，并且当电压与参考电压不同时，产生正常的时钟信号。 芯片组耦合到电压比较器的输出端。 当电压等于参考电压时，芯片组在双数据速率模式下运行。 如果电压与参考电压不同，则芯片组以正常数据速率模式运行。

公开(公告)号：US06756665B1

公开(公告)日：2004-06-29

申请号：US10635564

申请日：2003-08-07

申请人： Nai-Shung Chang

发明人： Nai-Shung Chang

IPC分类号： H01L2352

CPC分类号： H01L24/49 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49111 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599

摘要： An integrated circuit (IC) package structure with heat dissipation design. The IC chip is disposed on a package substrate and a power ring structure surrounds the chip. Due to the relatively large surface area of the power ring structure near the high heat zone of the IC chip, the contact area between the power ring structure and package substrate is enlarged. The power ring structure is connected to the isoelectric conductive layer of a multi-layer circuit board via an electric connection path, thereby enhancing heat dissipation.

摘要翻译： 具有散热设计的集成电路（IC）封装结构。 IC芯片设置在封装基板上，电源环结构围绕芯片。 由于IC芯片的高热区附近的功率环结构的表面积相对较大，所以功率环结构与封装基板之间的接触面积增大。 功率环结构通过电连接路径连接到多层电路板的等电导电层，从而增强散热。

公开(公告)号：US06590827B2

公开(公告)日：2003-07-08

申请号：US09955781

申请日：2001-09-19

申请人： Nai-Shung Chang ,  Jin-Cheng Huang

发明人： Nai-Shung Chang ,  Jin-Cheng Huang

IPC分类号： G11C800

CPC分类号： G11C7/225 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  H03K5/151

摘要： A clock circuit for supporting a plurality of memory module types is provided. The clock circuit is connected to a first type memory module slot, and a second type memory module slot. The clock circuit includes a clock generator for producing a clock signal and a clock buffer having doubly defined clock pins for outputting the first type memory clock signal or the second type memory clock signal. The clock buffer receives the clock signal and outputs a first type memory clock signal to the first type memory clock pin. The doubly defined clock pin is also capable of outputting a second type memory clock signal to the second type memory clock pin. This invention is capable of using just a single clock buffer to drive a plurality of different memory module types.

公开(公告)号：US06554195B1

公开(公告)日：2003-04-29

申请号：US09422020

申请日：1999-10-20

申请人： Nai-Shung Chang ,  Lie-Wen Chen ,  Ching-Fu Chuang ,  Chia-Hsing Yu

发明人： Nai-Shung Chang ,  Lie-Wen Chen ,  Ching-Fu Chuang ,  Chia-Hsing Yu

IPC分类号： G06K1906

CPC分类号： G06F1/185 ,  G06F1/184 ,  G06F1/186 ,  H05K1/023 ,  H05K1/0262 ,  H05K1/117 ,  H05K1/141 ,  H05K3/368 ,  H05K7/1092 ,  H05K2201/10022 ,  H05K2201/10196 ,  H05K2201/10325 ,  H05K2201/10689

摘要： A dual processor adapter card with a plurality of electrical pins for inserting into a processor slot on a mainboard by which the adapter card is electrically coupled to the mainboard. There is a first and a second processor socket on the adapter card for carrying a first and a second processor respectively. The first and the second processor socket each has a plurality of corresponding pins, a portion of the pins of the first and the second processor socket corresponds to a portion of the electrical pins. Corresponding pins are coupled together. Furthermore, each of the pins that act as a terminal lead in the first and the second processor socket is connected to a pull-up resistor, and the pull-up resistor is connected to a terminal voltage. In addition, a zero-delay buffer for synchronizing clock pulse signals and a voltage regulator for regulating a power voltage into a suitable working voltage are mounted on the adapter card and coupled to the first and the second processor socket respectively.

摘要翻译： 一种双处理器适配器卡，其具有多个电引脚，用于插入到主板上的处理器插槽中，通过该处理器插槽将适配器卡电耦合到主板。 适配器卡上有一个第一和第二个处理器插座，分别用于承载第一和第二处理器。 第一和第二处理器插座各自具有多个对应的引脚，第一和第二处理器插座的一部分引脚对应于电引脚的一部分。 相应的引脚耦合在一起。 此外，在第一和第二处理器插座中用作端子引线的每个引脚连接到上拉电阻器，并且上拉电阻器连接到端子电压。 此外，用于将时钟脉冲信号同步的零延迟缓冲器和用于将电源电压调节到合适工作电压的电压调节器分别安装在适配器卡上并分别耦合到第一和第二处理器插槽。

公开(公告)号：US06528872B2

公开(公告)日：2003-03-04

申请号：US10127082

申请日：2002-04-19

申请人： Nai-Shung Chang

发明人： Nai-Shung Chang

IPC分类号： H01L2352

CPC分类号： H01L23/49838 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5383 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48237 ,  H01L2224/49111 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/30107 ,  H05K1/0216 ,  H05K1/181 ,  H05K2201/0792 ,  H05K2201/094 ,  H05K2201/10522 ,  H05K2201/10689 ,  H05K2203/049 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A ball grid array packaging structure for sealing a silicon chip on a substrate is disclosed. The substrate includes a front wiring layer and a back wiring layer. The front wiring layer includes a plurality of inner power rings and an outer power ring. The inner power rings are attached and together they surround a central region where the silicon chip is attached. The inner power rings and the outer power ring have a substantially identical width and the outer power ring surrounds all the inner power rings. The back wiring layer has a large number of interface power balls and core power balls. The interface power balls may be further subdivided into groups of inner power balls, while each group of inner power balls corresponds and couples with one of the inner power rings of the front wiring layer. The core power balls connect with the outer power ring and surround the interface power balls.

公开(公告)号：US06502196B1

公开(公告)日：2002-12-31

申请号：US09436590

申请日：1999-11-09

申请人： Nai-Shung Chang ,  Jang-Lih Hsieh

发明人： Nai-Shung Chang ,  Jang-Lih Hsieh

IPC分类号： G06F126

CPC分类号： G06F1/3296 ,  G06F1/3203 ,  Y02D10/172

摘要： A voltage converter for supporting a suspension-to-RAM (STR) mode of power management. The voltage converter has a flip-flop, a resume & initialization logic circuit for producing a resume signal, a STR logic circuit for producing a STR signal, a first voltage-conversion unit and a second voltage-conversion unit. An output terminal of the resume & initialization logic circuit is connected to a first input terminal of the flip-flop. An output terminal of the STR logic circuit is connected to a second input terminal of the flip-flop. An output terminal of the flip-flop is connected to the first voltage-conversion unit, and a complementary output terminal of the flip-flop is connected to the second voltage-conversion unit. A suspension voltage or a power voltage is applied to the voltage pin of a system memory depending on the mode of power management.

摘要翻译： 一种用于支持电源管理的悬挂到RAM（STR）模式的电压转换器。 电压转换器具有触发器，用于产生恢复信号的恢复和初始化逻辑电路，用于产生STR信号的STR逻辑电路，第一电压转换单元和第二电压转换单元。 恢复和初始化逻辑电路的输出端连接到触发器的第一输入端。 STR逻辑电路的输出端连接到触发器的第二输入端。 触发器的输出端子连接到第一电压转换单元，并且触发器的互补输出端子连接到第二电压转换单元。 取决于电源管理的模式，将悬架电压或电源电压施加到系统存储器的电压引脚。