公开(公告)号：US08435802B2

公开(公告)日：2013-05-07

申请号：US11438127

申请日：2006-05-22

申请人： Min-Hwa Chi ,  Tai-Chun Huang ,  Chih-Hsiang Yao

发明人： Min-Hwa Chi ,  Tai-Chun Huang ,  Chih-Hsiang Yao

IPC分类号： H01L21/00

CPC分类号： H01L21/76898 ,  H01L21/768 ,  H01L23/528 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is prepared by an annealing process to interconnect at least two components of the device by a conductor line surrounded by an insulator material. The annealing process results in formation of residual stresses within the conductor line and the insulator material. A notch is designed in the layout on a selective portion of the mask for patterning conductor line. The existence of a shape of notch on the selective portion generates extra stress components within the conductor line than if without the existence of the notch. The position of the notch is selected so that the extra stress components substantially counteract the residual stresses, thereby causing a net reduction in the residual stresses. The reduction in the residual stresses results in a corresponding mechanical stress migration and therefore improvement in the reliability of the device.

摘要翻译： 通过退火工艺制备半导体器件，通过由绝缘体材料包围的导体线来互连器件的至少两个部件。 退火过程导致在导线和绝缘体材料内形成残余应力。 在掩模的选择性部分上的布局中设计凹口，用于图案化导体线。 选择部分上的凹口形状的存在在不存在凹口的情况下，在导线内产生额外的应力分量。 选择凹口的位置使得额外的应力分量基本上抵消残余应力，从而导致残余应力的净减小。 残余应力的减小导致相应的机械应力迁移，从而提高了装置的可靠性。

公开(公告)号：US07994040B2

公开(公告)日：2011-08-09

申请号：US11785023

申请日：2007-04-13

申请人： Min-Hwa Chi ,  Wen-Chuan Chiang ,  Mu-Chi Chiang ,  Chang-Ku Chen

发明人： Min-Hwa Chi ,  Wen-Chuan Chiang ,  Mu-Chi Chiang ,  Chang-Ku Chen

IPC分类号： H01L21/4763

CPC分类号： H01L29/665 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  Y02P80/30

摘要： A method for forming a semiconductor device is disclosed. A substrate including a gate dielectric layer and a gate electrode layer sequentially formed thereon is provided. An offset spacer is formed on sidewalls of the gate dielectric layer and the gate electrode layer. A carbon spacer is formed on a sidewall of the offset spacer, and the carbon spacer is then removed. The substrate is implanted to form a lightly doped region using the gate electrode layer and the offset spacer as a mask. The method may also include providing a substrate having a gate dielectric layer and a gate electrode layer sequentially formed thereon. A liner layer is formed on sidewalls of the gate electrode layer and on the substrate. A carbon spacer is formed on a portion of the liner layer adjacent the sidewall of the gate electrode layer. A main spacer is formed on a sidewall of the carbon spacer. The carbon spacer is removed to form an opening between the liner layer and the main spacer. The opening is sealed by a sealing layer to form an air gap.

摘要翻译： 公开了一种用于形成半导体器件的方法。 提供了包括顺序地形成在其上的栅介电层和栅极电极层的基板。 在栅极电介质层和栅极电极层的侧壁上形成偏移间隔物。 在间隔物的侧壁上形成碳隔离物，然后除去碳隔离物。 使用栅极电极层和偏移间隔物作为掩模，注入衬底以形成轻掺杂区域。 该方法还可以包括提供具有顺序地形成在其上的栅极电介质层和栅极电极层的衬底。 衬底层形成在栅电极层的侧壁和衬底上。 在衬垫层的与栅电极层的侧壁相邻的部分上形成碳隔离物。 主间隔件形成在碳隔离件的侧壁上。 去除碳间隔物以在衬垫层和主间隔物之间​​形成开口。 开口由密封层密封以形成气隙。

公开(公告)号：US07498657B2

公开(公告)日：2009-03-03

申请号：US11102340

申请日：2005-04-08

申请人： Min-Hwa Chi

发明人： Min-Hwa Chi

IPC分类号： H01L29/00

CPC分类号： H01L27/0802 ,  H01L29/7722 ,  H01L29/8083 ,  H01L29/8605

摘要： A vertical resistor. A substrate includes a trench filled by an isolation layer. A first doped-type region and a second doped-type region are formed on both sides of the trench. The first doped-type region receives a control bias, the second doped-type region receives a reference bias, and a resistance between the second doped-type region and the substrate is adjusted in response to a voltage difference between the control bias and the reference bias.

摘要翻译： 一个垂直电阻。 衬底包括由隔离层填充的沟槽。 第一掺杂型区域和第二掺杂型区域形成在沟槽的两侧。 第一掺杂型区域接收控制偏压，第二掺杂型区域接收参考偏置，并且响应于控制偏压和参考电压之间的电压差来调整第二掺杂型区域和衬底之间的电阻 偏压。

公开(公告)号：US07320926B2

公开(公告)日：2008-01-22

申请号：US11339874

申请日：2006-01-26

申请人： Min-Hwa Chi

发明人： Min-Hwa Chi

IPC分类号： H01L21/76 ,  H01L21/20

CPC分类号： H01L21/823807 ,  H01L21/76224 ,  H01L21/823878 ,  H01L21/823885 ,  H01L27/0805 ,  H01L27/092 ,  H01L28/40 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/4916 ,  H01L29/517 ,  H01L29/66181 ,  H01L29/781 ,  H01L29/7846

摘要： A method for forming shallow trenches having different trench fill materials is described. A stop layer is provided on a substrate. A plurality of trenches is etched through the stop layer and into the substrate. A first layer is deposited over the stop layer and filling said trenches. The first layer is planarized to the stop layer leaving the first layer within the trenches. The first layer is removed from a subset of the trenches. A second layer is deposited over the stop layer and within the subset of trenches and planarized to the stop layer leaving the second layer within the subset of trenches to complete fabrication of shallow trenches having different trench fill materials. The trench fill materials may be dielectric layers having different dielectric constants or they may be a dielectric layer and a conducting layer. The method can be extended to provide three or more different trench fill materials.

摘要翻译： 描述了形成具有不同沟槽填充材料的浅沟槽的方法。 在基板上设置停止层。 通过阻挡层蚀刻多个沟槽并进入衬底。 第一层沉积在停止层上并填充所述沟槽。 第一层被平坦化到停留层，离开沟槽内的第一层。 从沟槽的子集中移除第一层。 第二层沉积在阻挡层上并且在沟槽的子集内并且平坦化到停止层，离开沟槽子集内的第二层，以完成具有不同沟槽填充材料的浅沟槽的制造。 沟槽填充材料可以是具有不同介电常数的介电层，或者它们可以是电介质层和导电层。 该方法可以扩展以提供三种或更多种不同的沟槽填充材料。

公开(公告)号：US07106088B2

公开(公告)日：2006-09-12

申请号：US11077463

申请日：2005-03-10

申请人： Ching-Wei Tsai ,  Chih-Hao Wang ,  Min-Hwa Chi

发明人： Ching-Wei Tsai ,  Chih-Hao Wang ,  Min-Hwa Chi

IPC分类号： G01R31/26

CPC分类号： G01R31/2621 ,  G01R31/2642

摘要： A preferred embodiment of the invention provides a method for testing a MISFET to determine the effect of hot carrier injection (HCI) on integrated circuit lifetime. The method comprises applying a positive stress voltage to a gate having a high-k dielectric, while simultaneously holding a drain voltage equal to the stress voltage. Using a stress voltage that is greater than a normal operating voltage accelerates the degradation and failure of the integrated circuit. Embodiments include monitoring electrical parameters such as threshold voltage, transconductance, linear drain current, or saturation drain current. A pre-selected shift in a monitored electrical parameter indicates device failure. Embodiments include analyzing the data by plotting the logarithm of an accelerated device lifetime versus the gate stress voltage. The device lifetime under operating conditions is predicted by extrapolating the plot for a given device operating voltage.

摘要翻译： 本发明的优选实施例提供了一种用于测试MISFET以确定热载流子注入（HCI）对集成电路寿命的影响的方法。 该方法包括对具有高k电介质的栅极施加正应力电压，同时保持等于应力电压的漏极电压。 使用大于正常工作电压的应力电压可加速集成电路的劣化和故障。 实施例包括监测诸如阈值电压，跨导，线性漏极电流或饱和漏极电流之类的电参数。 受监控的电气参数中的预选位移表示设备故障。 实施例包括通过绘制加速器件寿命与栅极应力电压的对数来分析数据。 在运行条件下的器件寿命通过外推给定器件工作电压的曲线来预测。

公开(公告)号：US20060158210A1

公开(公告)日：2006-07-20

申请号：US11077463

申请日：2005-03-10

申请人： Ching-Wei Tsai ,  Chih-Hao Wang ,  Min-Hwa Chi

发明人： Ching-Wei Tsai ,  Chih-Hao Wang ,  Min-Hwa Chi

IPC分类号： G01R31/26

CPC分类号： G01R31/2621 ,  G01R31/2642

摘要： A preferred embodiment of the invention provides a method for testing a MISFET to determine the effect of hot carrier injection (HCI) on integrated circuit lifetime. The method comprises applying a positive stress voltage to a gate having a high-k dielectric, while simultaneously holding a drain voltage equal to the stress voltage. Using a stress voltage that is greater than a normal operating voltage accelerates the degradation and failure of the integrated circuit. Embodiments include monitoring electrical parameters such as threshold voltage, transconductance, linear drain current, or saturation drain current. A pre-selected shift in a monitored electrical parameter indicates device failure. Embodiments include analyzing the data by plotting the logarithm of an accelerated device lifetime versus the gate stress voltage. The device lifetime under operating conditions is predicted by extrapolating the plot for a given device operating voltage.

摘要翻译： 本发明的优选实施例提供了一种用于测试MISFET以确定热载流子注入（HCI）对集成电路寿命的影响的方法。 该方法包括对具有高k电介质的栅极施加正应力电压，同时保持等于应力电压的漏极电压。 使用大于正常工作电压的应力电压可加速集成电路的劣化和故障。 实施例包括监测诸如阈值电压，跨导，线性漏极电流或饱和漏极电流之类的电参数。 受监控的电气参数中的预选位移表示设备故障。 实施例包括通过绘制加速器件寿命与栅极应力电压的对数来分析数据。 在运行条件下的器件寿命通过外推给定器件工作电压的曲线来预测。

公开(公告)号：US20060121394A1

公开(公告)日：2006-06-08

申请号：US11339874

申请日：2006-01-26

申请人： Min-Hwa Chi

发明人： Min-Hwa Chi

IPC分类号： G03F7/00

CPC分类号： H01L21/823807 ,  H01L21/76224 ,  H01L21/823878 ,  H01L21/823885 ,  H01L27/0805 ,  H01L27/092 ,  H01L28/40 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/4916 ,  H01L29/517 ,  H01L29/66181 ,  H01L29/781 ,  H01L29/7846

摘要： A method for forming shallow trenches having different trench fill materials is described. A stop layer is provided on a substrate. A plurality of trenches is etched through the stop layer and into the substrate. A first layer is deposited over the stop layer and filling said trenches. The first layer is planarized to the stop layer leaving the first layer within the trenches. The first layer is removed from a subset of the trenches. A second layer is deposited over the stop layer and within the subset of trenches and planarized to the stop layer leaving the second layer within the subset of trenches to complete fabrication of shallow trenches having different trench fill materials. The trench fill materials may be dielectric layers having different dielectric constants or they may be a dielectric layer and a conducting layer. The method can be extended to provide three or more different trench fill materials.

摘要翻译： 描述了形成具有不同沟槽填充材料的浅沟槽的方法。 在基板上设置停止层。 通过阻挡层蚀刻多个沟槽并进入衬底。 第一层沉积在停止层上并填充所述沟槽。 第一层被平坦化到停留层，离开沟槽内的第一层。 从沟槽的子集中移除第一层。 第二层沉积在阻挡层上并且在沟槽的子集内并且平坦化到停止层，离开沟槽子集内的第二层，以完成具有不同沟槽填充材料的浅沟槽的制造。 沟槽填充材料可以是具有不同介电常数的介电层，或者它们可以是电介质层和导电层。 该方法可以扩展以提供三种或更多种不同的沟槽填充材料。

公开(公告)号：US06949471B2

公开(公告)日：2005-09-27

申请号：US10631251

申请日：2003-07-31

申请人： Ching-Chen Hao ,  Hung-Jen Lin ,  Min-Hwa Chi ,  Chih-Heng Shen

发明人： Ching-Chen Hao ,  Hung-Jen Lin ,  Min-Hwa Chi ,  Chih-Heng Shen

IPC分类号： H01L21/027 ,  H01L21/28 ,  H01L21/283 ,  H01L21/31 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L21/28211 ,  H01L21/28035 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/32139 ,  H01L21/823828

摘要： A method of fabricating polysilicon patterns. The method includes depositing polysilicon on a substrate. The polysilicon may be doped or pre-doped depending upon the application. A mask layer is applied and patterned. Thereafter, the polysilicon is etched to form the polysilicon patterns and an oxidizing step is performed. The mask layer is removed after the oxidizing step is performed.

公开(公告)号：US06855587B2

公开(公告)日：2005-02-15

申请号：US10696430

申请日：2003-10-29

申请人： Min-Hwa Chi

发明人： Min-Hwa Chi

IPC分类号： H01L29/739 ,  H01L29/864 ,  H01L21/337

CPC分类号： H01L29/864 ,  H01L29/7391

摘要： A new gate-controlled, negative resistance diode device is achieved. The device comprises, first, a semiconductor layer in a substrate. The semiconductor layer contains an emitter region and a barrier region. The barrier region is in contact with the emitter region and is laterally adjacent to the emitter region. The semiconductor layer contains a collector region. A drift region comprises the semiconductor layer between the barrier region and the collector region. Finally, a gate comprises a conductor layer overlying the drift region, the barrier region, and at least a part of the emitter region with an insulating layer therebetween. A method of manufacture is achieved.

摘要翻译： 实现了新的栅极控制的负电阻二极管器件。 该器件首先包括衬底中的半导体层。 半导体层包含发射极区域和阻挡区域。 阻挡区域与发射极区域接触并且横向邻近发射极区域。 半导体层包含收集区域。 漂移区域包括位于阻挡区域和集电极区域之间的半导体层。 最后，栅极包括覆盖漂移区域，势垒区域的导体层以及发射极区域之间具有绝缘层的至少一部分。 实现了制造方法。

公开(公告)号：US06579791B1

公开(公告)日：2003-06-17

申请号：US10074909

申请日：2002-02-12

申请人： Yeur Luen Tu ,  Chia-Shiung Tsai ,  Min-Hwa Chi

发明人： Yeur Luen Tu ,  Chia-Shiung Tsai ,  Min-Hwa Chi

IPC分类号： H01L214763

CPC分类号： H01L21/76808

摘要： A method of fabricating a dual damascene opening, comprising the following sequential steps. A structure having a stop layer formed over a second low-k material layer formed over a stop layer formed over a first low-k material layer is provided. These layers are etched to form a via opening exposing a portion of the structure. A photoresist layer is formed over the second low-k material layer stop layer and filling the via opening. The photoresist layer having a treated upper portion including a central trench pattern area that is wider than, and substantially centered over, the via opening. The treated upper portion of the photoresist layer preventing any effects to the underlying photoresist layer so that the underlying photoresist layer does not deleteriously interact with the first or second low-k material layer. Removing: (1) the central trench pattern area of the upper treated portion of the photoresist and the photoresist under the central trench pattern area a to form a trench pattern opening exposing a portion of the second low-k material layer stop layer under the removed central trench pattern area; and (2) the photoresist layer within the via opening while leaving a portion of the photoresist layer within the via opening overlying the portion of the structure that was exposed by the via opening. Transferring the trench pattern opening to the second low-k material layer stop layer and the second low-k material layer to form a trench substantially centered over the remaining via opening and completing the dual damascene opening.

摘要翻译： 一种制造双镶嵌开口的方法，包括以下顺序步骤。 提供一种具有形成在形成在第一低k材料层上形成的停止层上的第二低k材料层上的停止层的结构。 蚀刻这些层以形成露出结构的一部分的通孔。 在第二低k材料层停止层上形成光致抗蚀剂层并填充通孔。 光致抗蚀剂层具有经处理的上部，其包括中心沟槽图案区域，该中心沟槽图案区域比通孔开口宽，并且基本上居中。 光致抗蚀剂层的经处理的上部防止对下面的光致抗蚀剂层的任何影响，使得下面的光致抗蚀剂层不会与第一或第二低k材料层有害地相互作用。 去除：（1）光致抗蚀剂的上部处理部分的中心沟槽图案区域和在中心沟槽图案区域a下方的光致抗蚀剂，以形成沟槽图形开口，暴露出被去除的第二低k材料层停止层的一部分 中央沟槽图案区; 和（2）通孔开口内的光致抗蚀剂层，同时留下通孔开口内的一部分光致抗蚀剂层，覆盖由通孔开口暴露的结构部分。 将沟槽图案开口转移到第二低k材料层停止层和第二低k材料层，以形成基本上位于剩余通孔开口上方的沟槽，并完成双镶嵌开口。