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41.
公开(公告)号:US11782572B2
公开(公告)日:2023-10-10
申请号:US16889584
申请日:2020-06-01
Applicant: Intel Corporation
Inventor: Glen J. Anderson , Carl S. Marshall , Jeffrey R. Jackson , Selvakumar Panneer , Andrea E. Johnson
IPC: G06F3/00 , G06F3/04817 , G06F16/54 , G06F16/58 , G06F3/01
CPC classification number: G06F3/04817 , G06F3/005 , G06F3/011 , G06F3/015 , G06F16/54 , G06F16/5866
Abstract: Apparatuses, methods, and storage medium associated with a browser for prioritized display of videos and/or photographs are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to operate a browser to present a plurality of photos and/or videos for viewing. A subset of the plurality of the photos and/or videos may be selected based on the results of an analysis of sensor data collected by a plurality of wearable sensors. The subset of the plurality of the photos and/or videos may be prioritized over other photos and/or videos from the plurality of the photos and/or videos in terms of presentation space allocated for presentation.
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公开(公告)号:US11698964B2
公开(公告)日:2023-07-11
申请号:US16650643
申请日:2017-12-13
Applicant: INTEL CORPORATION
Inventor: Danyu Bi , Salmin Sultana , Yuanyuan Li , Yong Jiang , Pramod Pesara , Selvakumar Panneer , Ravi Sahita
CPC classification number: G06F21/56 , G06F9/30061 , G06F9/448 , G06F11/3636 , G06F12/1009 , G06F21/566 , H04L63/145 , H04L63/1441
Abstract: A system for detecting malware includes a processor to collect processor trace information corresponding to an application being executed by the processor (202). The processor can also detect an invalid indirect branch instruction from the processor trace information (204) and detect at least one malware instruction being executed by the application in response to analyzing modified memory values corresponding to the invalid indirect branch (206). Additionally, the processor can block the application from accessing or modifying memory (208).
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公开(公告)号:US20220383580A1
公开(公告)日:2022-12-01
申请号:US17514485
申请日:2021-10-29
Applicant: Intel Corporation
Inventor: Honnesh Rohmetra , Carl S. Marshall , Selvakumar Panneer
Abstract: One embodiment provides a method comprising, at a runtime library executed by a processor of a data processing system, receiving an input frame having objects to be stylized via a style transfer network associated with the runtime library, wherein the style transfer network is a neural network model trained to apply one or more visual styles to an input frame, performing instance segmentation on the input frame to generate one or more instance masks to identify one or more objects to be stylized, generating one or more stylized frames for each style to transfer to the input frame, and merging, via the one or more instance masks, stylized objects from one or more stylized frames with un-stylized content from the input frame to generate an output frame with per-instance stylization.
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公开(公告)号:US11417236B2
公开(公告)日:2022-08-16
申请号:US16235448
申请日:2018-12-28
Applicant: Intel Corporation
Inventor: Carl S. Marshall , Giuseppe Raffa , Shi Meng , Lama Nachman , Ankur Agrawal , Selvakumar Panneer , Glen J. Anderson , Lenitra M. Durham
IPC: G09B19/06 , G09B7/02 , G06F16/907 , G06F16/9035 , G06F40/30 , G06V20/20
Abstract: Language education systems capable of integrating with a user's daily life and automatically producing educational prompts would be particularly advantageous. An example method includes determining a user's identity, detecting a language education subject, prompting the user with a language education message, receiving a user's response, and updating a user profile associated with the user based on the user's response. Methods may also include determining user state (including emotional, physical, social, etc.) and determining, based on the user state, whether to prompt the user with the language education prompt.
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公开(公告)号:US20220100583A1
公开(公告)日:2022-03-31
申请号:US17532562
申请日:2021-11-22
Applicant: Intel Corporation
Inventor: Reshma Lal , Pradeep Pappachan , Luis Kida , Soham Jayesh Desai , Sujoy Sen , Selvakumar Panneer , Robert Sharp
Abstract: An apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. The apparatus includes a programmable integrated circuit (IC) comprising secure device manager (SDM) hardware circuitry to: receive a tenant bitstream of a tenant and a tenant use policy for utilization of the programmable IC via the tenant bitstream, wherein the tenant use policy is cryptographically bound to the tenant bitstream by a cloud service provider (CSP) authorizing entity and signed with a signature of the CSP authorizing entity; in response to successfully verifying the signature, extract the tenant use policy to provide to a policy manager of the programmable IC for verification; in response to the policy manager verifying the tenant bitstream based on the tenant use policy, configure a partial reconfiguration (PR) region of the programable IC using the tenant bitstream; and associate a slot ID of the PR region with the tenant use policy.
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公开(公告)号:US20220100579A1
公开(公告)日:2022-03-31
申请号:US17525143
申请日:2021-11-12
Applicant: Intel Corporation
Inventor: Reshma Lal , Pradeep Pappachan , Luis Kida , Soham Jayesh Desai , Sujoy Sen , Selvakumar Panneer , Robert Sharp
Abstract: An apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. The apparatus includes a source remote direct memory access (RDMA) network interface controller (RNIC); a queue to store a data entry corresponding to an RDMA request between the source RNIC and a sink RNIC; a data buffer to store data for an RDMA transfer corresponding to the RDMA request, the RDMA transfer between the source RNIC and the sink RNIC; and a trusted execution environment (TEE) comprising an authentication tag controller to: initialize a first authentication tag calculated using a first key known between a source consumer generating the RDMA request and the source RNIC; associate the first authentication tag with the data entry as integrity verification; initialize a second authentication tag calculated using a second key; and associate the second authentication tag with the data buffer as integrity verification for the data buffer.
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公开(公告)号:US11217126B2
公开(公告)日:2022-01-04
申请号:US15857550
申请日:2017-12-28
Applicant: Intel Corporation
Inventor: Carl S. Marshall , John Sherry , Giuseppe Raffa , Glen J. Anderson , Selvakumar Panneer , Daniel Pohl
Abstract: The disclosed embodiments generally relate to methods, systems and apparatuses to provide ad hoc digital signage for public or private display. In certain embodiments, the disclosure provides dynamically formed digital signage. In one application, one or more drones are used to project the desired signage. In another application one or more drones are used to form a background to receive the projected image. In still another application, sensors are used to detect audience movement, line of sight or engagement level. The sensor information is then used to arrange the projecting drones or the surface-image drones to further signage presentation.
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公开(公告)号:US20210390664A1
公开(公告)日:2021-12-16
申请号:US16898116
申请日:2020-06-10
Applicant: Intel Corporation
Inventor: Daniel Pohl , Carl Marshall , Selvakumar Panneer
Abstract: An apparatus to facilitate deep learning based selection of samples for adaptive supersampling is disclosed. The apparatus includes one or more processing elements to: receive training data comprising input tiles and corresponding supersampling values for the input tiles, wherein each input tile comprises a plurality of pixels, and train, based on the training data, a machine learning model to identify a level of supersampling for a rendered tile of pixels.
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公开(公告)号:US11151769B2
公开(公告)日:2021-10-19
申请号:US16537140
申请日:2019-08-09
Applicant: Intel Corporation
Inventor: Hugues Labbe , Darrel Palke , Sherine Abdelhak , Jill Boyce , Varghese George , Scott Janus , Adam Lake , Zhijun Lei , Zhengmin Li , Mike Macpherson , Carl Marshall , Selvakumar Panneer , Prasoonkumar Surti , Karthik Veeramani , Deepak Vembar , Vallabhajosyula Srinivasa Somayazulu
Abstract: One embodiment provides for a graphics processor comprising a block of graphics compute units, a graphics processor pipeline coupled to the block of graphics compute units, and a programmable neural network unit including one or more neural network hardware blocks. The programmable neural network unit is coupled with the block of graphics compute units and the graphics processor pipeline. The one or more neural network hardware blocks include hardware to perform neural network operations and activation operations for a layer of a neural network. The programmable neural network unit can configure settings of one or more hardware blocks within the graphics processor pipeline based on a machine learning model trained to optimize performance of a set of workloads.
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公开(公告)号:US20210097639A1
公开(公告)日:2021-04-01
申请号:US16583478
申请日:2019-09-26
Applicant: Intel Corporation
Inventor: Abhishek Venkatesh , Selvakumar Panneer
Abstract: Embodiments described herein are generally directed to conservative rasterization pipeline configurations that allow EarlyZ to be enabled for conservative rasterization. An embodiment of a method includes receiving, by a conservative rasterizer, a primitive; creating, by the conservative rasterizer, a pixel location stream based on the primitive and inner coverage data for each pixel within the pixel location stream indicative of whether the corresponding pixel is fully covered or partially covered by the primitive; for each block of pixels of the pixel location stream, launching, by the conservative rasterizer, a thread of a pixel shader, including causing EarlyZ to be performed or not for fully covered pixels and partially covered pixels, respectively; and generating, by the pixel shader, a stream of pixel updates by conditionally processing the pixel location stream to incorporate pixel shading characteristics, including for partially covered pixels computing a depth value and causing LateZ to be performed.
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