Unclonable ID based chip-to-chip communication
    45.
    发明授权
    Unclonable ID based chip-to-chip communication 有权
    不可克隆的基于ID的芯片到芯片通信

    公开(公告)号:US09219722B2

    公开(公告)日:2015-12-22

    申请号:US14102607

    申请日:2013-12-11

    CPC classification number: H04L63/08 G06F21/31 H04L9/3278 H04L63/0876

    Abstract: A first copy of an intrinsic ID of a first node may be stored on a second node. The first node may receive a challenge that causes it to generate a second copy of its intrinsic ID. The second copy and a random value may be used as inputs of a function to generate a first code. The first code is transmitted to the second node. The second node decodes the first code using its local copies of the random value and/or the intrinsic ID. The second node checks the decoded information against its local information and authenticates the first node if there is a match.

    Abstract translation: 可以将第一节点的内部ID的第一副本存储在第二节点上。 第一个节点可能会接收一个挑战,导致它产生其内在ID的第二个副本。 第二副本和随机值可以用作函数的输入以产生第一代码。 第一个代码被传送到第二个节点。 第二个节点使用其随机值和/或固有ID的本地副本解码第一个代码。 第二节点根据其本地信息检查解码的信息,并且如果存在匹配则认证第一节点。

    PHYSICALLY UNCLONABLE FUSE USING A NOR TYPE MEMORY ARRAY
    46.
    发明申请
    PHYSICALLY UNCLONABLE FUSE USING A NOR TYPE MEMORY ARRAY 有权
    使用NOR型存储阵列的物理不可靠保险丝

    公开(公告)号:US20150278551A1

    公开(公告)日:2015-10-01

    申请号:US14224099

    申请日:2014-03-25

    Abstract: A method for identifying an unclonable chip uses hardware intrinsic keys and authentication responses employing intrinsic parameters of memory cells invariant and unique to the unclonable chip, wherein intrinsic parameters that characterize the chip can extend over its lifetime. The memory cells having a charge-trap behavior are arranged in an NOR type memory array, allowing to create a physically unclonable fuse (PUF) generation using non-programmed memory cells, while stringing non-volatile bits in programmed memory cells. The non-volatile memory cell bits are used for error-correction-code (ECC) for the generated PUF. The invention can further include a public identification using non-volatile bits, allowing hand shaking authentication using computer with dynamic challenge.

    Abstract translation: 用于识别不可克隆芯片的方法使用硬件本征密钥和认证响应,其使用不可克隆的芯片不变且唯一的存储器单元的固有参数,其中表征芯片的固有参数可以在其寿命内延伸。 具有电荷陷阱行为的存储单元被布置在NOR型存储器阵列中,允许使用非编程存储器单元产生物理上不可克隆的熔丝(PUF),同时在编程的存储器单元中串联非易失性位。 非易失性存储单元位用于生成的PUF的纠错码(ECC)。 本发明还可以包括使用非易失性位的公共识别,允许使用具有动态挑战的计算机进行手抖动认证。

    Self-authenticating of chip based on intrinsic features
    47.
    发明授权
    Self-authenticating of chip based on intrinsic features 有权
    基于内在特征的芯片自身认证

    公开(公告)号:US09038133B2

    公开(公告)日:2015-05-19

    申请号:US13707964

    申请日:2012-12-07

    Abstract: Embodiments of the present invention provide an authenticating service of a chip having an intrinsic identifier (ID). In a typical embodiment, an authenticating device is provided that includes an identification (ID) engine, a self-test engine, and an intrinsic component. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using the intrinsic feature, and stores the authentication value in memory. The self-test engine generates a second authentication value using an authentication challenge. The identification engine includes a compare circuitry that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values.

    Abstract translation: 本发明的实施例提供具有固有标识符(ID)的芯片的认证服务。 在典型的实施例中,提供了一种认证装置,其包括识别(ID)引擎,自检引擎和内在组件。 固有分量与芯片相关联并且包括固有特征。 自检引擎检索固有特征并将其传达给识别引擎。 识别引擎接收固有特征,使用本征特征生成第一认证值,并将认证值存储在存储器中。 自检引擎使用认证挑战生成第二认证值。 识别引擎包括比较电路,其比较第一认证值和第二认证值,并且基于两个值的比较结果生成认证输出值。

    Fabricating transmon qubit flip-chip structures for quantum computing devices

    公开(公告)号:US11489103B2

    公开(公告)日:2022-11-01

    申请号:US17128321

    申请日:2020-12-21

    Abstract: A quantum computing device is formed using a first chip and a second chip, the first chip having a first substrate, a first set of pads, and a set of Josephson junctions disposed on the first substrate. The second chip has a second substrate, a second set of pads disposed on the second substrate opposite the first set of pads, and a second layer formed on a subset of the second set of pads. The second layer is configured to bond the first chip and the second chip. The subset of the second set of pads corresponds to a subset of the set of Josephson junctions selected to avoid frequency collision between qubits in a set of qubits. A qubit is formed using a Josephson junction from the subset of Josephson junctions and another Josephson junction not in the subset being rendered unusable for forming qubits.

Patent Agency Ranking