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公开(公告)号:US20190165237A1
公开(公告)日:2019-05-30
申请号:US15822338
申请日:2017-11-27
Applicant: International Business Machines Corporation
Inventor: Jared Barney Hertzberg , Sami Rosenblatt , Rasit O. Topaloglu
IPC: H01L39/02 , H01L23/48 , H01L23/532 , H01L21/768 , H01L21/3205 , H01L39/24 , H01L39/22 , H03K19/195 , G06N99/00
CPC classification number: H01L39/025 , G06N10/00 , H01L21/32058 , H01L21/76877 , H01L21/76898 , H01L23/481 , H01L23/53285 , H01L23/5329 , H01L27/18 , H01L39/223 , H01L39/2493 , H03K19/195
Abstract: A capacitive coupling device (superconducting C-coupler) includes a trench formed through a substrate, from a backside of the substrate, reaching a depth in the substrate, substantially orthogonal to a plane of fabrication on a frontside of the substrate, the depth being less than a thickness of the substrate. A superconducting material is deposited as a continuous conducting via layer in the trench with a space between surfaces of the via layer in the trench remaining accessible from the backside. A superconducting pad is formed on the frontside, the superconducting pad coupling with a quantum logic circuit element fabricated on the frontside. An extension of the via layer is formed on the backside. The extension couples to a quantum readout circuit element fabricated on the backside.
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公开(公告)号:US10170681B1
公开(公告)日:2019-01-01
申请号:US15823713
申请日:2017-11-28
Applicant: International Business Machines Corporation
Inventor: Sami Rosenblatt , Jason S. Orcutt
Abstract: A qubit may be formed by forming a Josephson junction between two capacitive plates. The Josephson junction may be annealed with a thermal source. The thermal source may be a laser that generates a Gaussian beam. An axicon lens may be exposed to the Gaussian beam. Annealing the Josephson junction may alter the resistance of the Josephson junction.
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公开(公告)号:US10103144B1
公开(公告)日:2018-10-16
申请号:US15799247
申请日:2017-10-31
Applicant: International Business Machines Corporation
Inventor: Sami Rosenblatt , Rasit O. Topaloglu
IPC: H01L29/06 , H01L27/088 , H01L21/762 , H01L21/82 , H01L21/3105 , H01L21/02 , H01L29/165 , H01L29/16 , H01L29/51 , H01L21/8238 , H01L21/8234
Abstract: A semiconductor structure, such as a microchip that includes a finFET, includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls. The thickness of the 2D material sidewall may be tuned to achieve desired finFET band gap control. Neighboring fins of the semiconductor structure form fin wells. The semiconductor structure may include a fin cap upon each fin and the 2D material is formed upon the sidewalls of the fin and the bottom surface of the fin wells. The semiconductor structure may include a well-plug at the bottom of the fin wells and the 2D material is formed upon the sidewalls and upper surface of the fins. The semiconductor structure may include both fin caps and well-plugs such that the 2D material is formed upon the sidewalls of the fins.
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公开(公告)号:US20180017509A1
公开(公告)日:2018-01-18
申请号:US15212932
申请日:2016-07-18
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Dirk Pfeiffer , Sami Rosenblatt , Chandrasekara Kothandaraman
IPC: G01N23/223
Abstract: Methods and systems for generating an identifier include detecting emissions from a phosphor pattern with a sensor grid comprising one or more sensors when the phosphor pattern is stimulated with radiation. An output signal of each sensor in the sensor grid is compared to a threshold value to generate respective identifier bits. An identifier is generated from the identifier bits.
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公开(公告)号:US09219722B2
公开(公告)日:2015-12-22
申请号:US14102607
申请日:2013-12-11
Applicant: International Business Machines Corporation
Inventor: Srivatsan Chellappa , Toshiaki Kirihata , Sami Rosenblatt
CPC classification number: H04L63/08 , G06F21/31 , H04L9/3278 , H04L63/0876
Abstract: A first copy of an intrinsic ID of a first node may be stored on a second node. The first node may receive a challenge that causes it to generate a second copy of its intrinsic ID. The second copy and a random value may be used as inputs of a function to generate a first code. The first code is transmitted to the second node. The second node decodes the first code using its local copies of the random value and/or the intrinsic ID. The second node checks the decoded information against its local information and authenticates the first node if there is a match.
Abstract translation: 可以将第一节点的内部ID的第一副本存储在第二节点上。 第一个节点可能会接收一个挑战,导致它产生其内在ID的第二个副本。 第二副本和随机值可以用作函数的输入以产生第一代码。 第一个代码被传送到第二个节点。 第二个节点使用其随机值和/或固有ID的本地副本解码第一个代码。 第二节点根据其本地信息检查解码的信息,并且如果存在匹配则认证第一节点。
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46.
公开(公告)号:US20150278551A1
公开(公告)日:2015-10-01
申请号:US14224099
申请日:2014-03-25
Applicant: International Business Machines Corporation
Inventor: Subramanian S. Iyer , Toshiaki Kirihata , Chandrasekharan Kothandaraman , Derek H. Leu , Sami Rosenblatt
CPC classification number: G06F21/70 , G06F21/44 , G06F21/73 , G06F2221/2103 , G09C1/00 , G11C16/0466 , G11C16/20 , G11C16/22 , G11C16/24 , G11C16/28 , H04L9/0866 , H04L9/3278
Abstract: A method for identifying an unclonable chip uses hardware intrinsic keys and authentication responses employing intrinsic parameters of memory cells invariant and unique to the unclonable chip, wherein intrinsic parameters that characterize the chip can extend over its lifetime. The memory cells having a charge-trap behavior are arranged in an NOR type memory array, allowing to create a physically unclonable fuse (PUF) generation using non-programmed memory cells, while stringing non-volatile bits in programmed memory cells. The non-volatile memory cell bits are used for error-correction-code (ECC) for the generated PUF. The invention can further include a public identification using non-volatile bits, allowing hand shaking authentication using computer with dynamic challenge.
Abstract translation: 用于识别不可克隆芯片的方法使用硬件本征密钥和认证响应,其使用不可克隆的芯片不变且唯一的存储器单元的固有参数,其中表征芯片的固有参数可以在其寿命内延伸。 具有电荷陷阱行为的存储单元被布置在NOR型存储器阵列中,允许使用非编程存储器单元产生物理上不可克隆的熔丝(PUF),同时在编程的存储器单元中串联非易失性位。 非易失性存储单元位用于生成的PUF的纠错码(ECC)。 本发明还可以包括使用非易失性位的公共识别,允许使用具有动态挑战的计算机进行手抖动认证。
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47.
公开(公告)号:US09038133B2
公开(公告)日:2015-05-19
申请号:US13707964
申请日:2012-12-07
Applicant: International Business Machines Corporation
Inventor: Srivatsan Chellappa , Subramanian S. Iyer , Toshiaki Kirihata , Sami Rosenblatt
CPC classification number: G06F21/30 , G01C1/00 , G06F21/44 , G06F2221/2129 , G09C1/00 , G11B20/00086 , H04L9/3278 , H04L9/3281 , H04L63/08 , H04N1/32144
Abstract: Embodiments of the present invention provide an authenticating service of a chip having an intrinsic identifier (ID). In a typical embodiment, an authenticating device is provided that includes an identification (ID) engine, a self-test engine, and an intrinsic component. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using the intrinsic feature, and stores the authentication value in memory. The self-test engine generates a second authentication value using an authentication challenge. The identification engine includes a compare circuitry that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values.
Abstract translation: 本发明的实施例提供具有固有标识符(ID)的芯片的认证服务。 在典型的实施例中,提供了一种认证装置,其包括识别(ID)引擎,自检引擎和内在组件。 固有分量与芯片相关联并且包括固有特征。 自检引擎检索固有特征并将其传达给识别引擎。 识别引擎接收固有特征,使用本征特征生成第一认证值,并将认证值存储在存储器中。 自检引擎使用认证挑战生成第二认证值。 识别引擎包括比较电路,其比较第一认证值和第二认证值,并且基于两个值的比较结果生成认证输出值。
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公开(公告)号:US20250069887A1
公开(公告)日:2025-02-27
申请号:US18452963
申请日:2023-08-21
Applicant: International Business Machines Corporation
Inventor: Eric Zhang , Jason S. Orcutt , Jared Barney Hertzberg , Sami Rosenblatt , Yves Martin
Abstract: A method for performing a calibration process comprises performing laser annealing operations on a set of test superconducting tunnel junction devices using different combinations of laser power and anneal time, determining junction resistance shifts of the test superconducting tunnel junction devices as a result of the laser annealing operations, and utilizing the determined junction resistance shifts of the test superconducting tunnel junction to determine calibration data for configuring laser annealing operations for laser tuning superconducting tunnel junction devices corresponding to the test superconducting tunnel junction devices.
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公开(公告)号:US12035642B2
公开(公告)日:2024-07-09
申请号:US17078158
申请日:2020-10-23
Applicant: International Business Machines Corporation
Inventor: Markus Brink , Jared B. Hertzberg , Sami Rosenblatt
IPC: G11C11/44 , B82Y10/00 , G01R33/34 , G06N10/00 , G11C17/16 , G11C17/18 , H01L23/544 , H03H11/02 , H04L9/40 , H10N60/01 , H10N60/12 , H10N60/80 , H10N60/81 , H10N60/82 , H10N69/00
CPC classification number: H10N60/805 , G01R33/34023 , G11C11/44 , G11C17/16 , G11C17/18 , H01L23/544 , H03H11/02 , H04L63/0876 , H10N60/0912 , H10N60/12 , H10N60/815 , H10N60/82 , H10N69/00 , B82Y10/00 , G06N10/00 , H01L2223/54446
Abstract: A technique relates to a superconducting chip. Resonant units have resonant frequencies, and the resonant units are configured as superconducting resonators. Josephson junctions are in the resonant units, and one or more of the Josephson junctions have a shorted tunnel barrier.
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公开(公告)号:US11489103B2
公开(公告)日:2022-11-01
申请号:US17128321
申请日:2020-12-21
Applicant: International Business Machines Corporation
Inventor: Jerry M. Chow , Sami Rosenblatt
Abstract: A quantum computing device is formed using a first chip and a second chip, the first chip having a first substrate, a first set of pads, and a set of Josephson junctions disposed on the first substrate. The second chip has a second substrate, a second set of pads disposed on the second substrate opposite the first set of pads, and a second layer formed on a subset of the second set of pads. The second layer is configured to bond the first chip and the second chip. The subset of the second set of pads corresponds to a subset of the set of Josephson junctions selected to avoid frequency collision between qubits in a set of qubits. A qubit is formed using a Josephson junction from the subset of Josephson junctions and another Josephson junction not in the subset being rendered unusable for forming qubits.
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