公开(公告)号：US10692985B2

公开(公告)日：2020-06-23

申请号：US16282607

申请日：2019-02-22

Applicant: International Business Machines Corporation

Inventor： Nicolas J. Loubet ,  Sanjay C. Mehta ,  Vijay Narayanan ,  Muthumanickam Sankarapandian

IPC: H01L29/00 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/49 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66 ,  H01L29/10 ,  H01L29/775 ,  B82Y10/00

Abstract: A starting structure for forming a gate-all-around field effect transistor (FET) and a method of fabricating the gate-all-around FET. The method includes forming a stack of silicon nanosheets above a substrate forming an interfacial layer over the nanosheets depositing a high-k dielectric layer conformally on the interfacial layer. The method also includes depositing a layer of silicon nitride (SiN) above the high-k dielectric layer and performing reliability anneal after depositing the layer of SiN to crystalize the high-k dielectric layer.

公开(公告)号：US10672671B2

公开(公告)日：2020-06-02

申请号：US15649182

申请日：2017-07-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Martin M. Frank ,  Renee T. Mo ,  Vijay Narayanan

IPC: H01L21/8258 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8252 ,  H01L29/267 ,  H01L29/66 ,  H01L29/10 ,  H01L29/51

Abstract: Semiconductor devices and methods of forming the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region. The second semiconductor region is formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A semiconductor cap is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.

公开(公告)号：US20200066724A1

公开(公告)日：2020-02-27

申请号：US16671637

申请日：2019-11-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Martin M. Frank ,  Renee T. Mo ,  Vijay Narayanan ,  John Rozen

IPC: H01L27/092 ,  H01L21/8258 ,  H01L21/8238

Abstract: Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A gate dielectric layer is formed over one or more of the first and second channel regions. A nitrogen-containing layer is formed on the gate dielectric layer. A gate is formed on the gate dielectric.

公开(公告)号：US10553584B2

公开(公告)日：2020-02-04

申请号：US16012056

申请日：2018-06-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Martin M. Frank ,  Renee T. Mo ,  Vijay Narayanan ,  John Rozen

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/8258

Abstract: Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A gate dielectric layer is formed over one or more of the first and second channel regions. A nitrogen-containing layer is formed on the gate dielectric layer. A gate is formed on the gate dielectric.

公开(公告)号：US10541151B1

公开(公告)日：2020-01-21

申请号：US16033384

申请日：2018-07-12

Applicant: International Business Machines Corporation

Inventor： Kam-Leung Lee ,  Deborah A. Neumayer ,  Son Nguyen ,  Martin M. Frank ,  Vijay Narayanan

IPC: H01L21/20 ,  H01L21/324 ,  H01L21/768 ,  H01L21/02 ,  H01L49/02 ,  H01L23/522 ,  H01L45/00 ,  G06N3/063 ,  H01L27/11502 ,  H01L43/02

Abstract: A conformal disposable absorber is disclosed which is capable of providing efficient heat transfer to an embedded memory device during a localized absorber anneal, without adversary impacting the back-end-of-the-line (BEOL) structure. The disposable absorber is composed of an amorphous carbonitride material that can be designed to have a low reflection coefficient for laser/flash illumination, and a high extinction coefficient for efficient laser/flash illumination absorption. The disposable absorber is formed at a temperature of 400° C. or less.

公开(公告)号：US10529573B2

公开(公告)日：2020-01-07

申请号：US15950773

申请日：2018-04-11

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Pouya Hashemi ,  Hemanth Jagannathan ,  Choonghyun Lee ,  Vijay Narayanan

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L29/161 ,  H01L21/28 ,  H01L21/02 ,  H01L21/84 ,  H01L29/49

Abstract: Methods are provided to form pure silicon oxide layers on silicon-germanium (SiGe) layers, as well as an FET device having a pure silicon oxide interfacial layer of a metal gate structure formed on a SiGe channel layer of the FET device. For example, a method comprises growing a first silicon oxide layer on a surface of a SiGe layer using a first oxynitridation process, wherein the first silicon oxide layer comprises nitrogen. The first silicon oxide layer is removed, and a second silicon oxide layer is grown on the surface of the SiGe layer using a second oxynitridation process, which is substantially the same as the first oxynitridation process, wherein the second silicon oxide layer is substantially devoid of germanium oxide and nitrogen. For example, the first silicon oxide layer comprises a SiON layer and the second silicon oxide layer comprises a pure silicon dioxide layer.

公开(公告)号：US10312157B2

公开(公告)日：2019-06-04

申请号：US15795414

申请日：2017-10-27

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan

IPC: H01L27/092 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/8238

Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.

公开(公告)号：US10217834B2

公开(公告)日：2019-02-26

申请号：US15684263

申请日：2017-08-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  ULVAC, Inc.

Inventor： Vijay Narayanan ,  Yohei Ogawa ,  John Rozen

IPC: H01L29/51 ,  H01L29/423 ,  H01L21/28 ,  H01L29/20 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L29/06 ,  H01L29/78

Abstract: A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer.

公开(公告)号：US20180337098A1

公开(公告)日：2018-11-22

申请号：US15813958

申请日：2017-11-15

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Hemanth Jagannathan ,  ChoongHyun Lee ,  Vijay Narayanan

IPC: H01L21/8238 ,  H01L29/49 ,  H01L29/161 ,  H01L29/16 ,  H01L29/10 ,  H01L29/06 ,  H01L21/02 ,  H01L21/324 ,  H01L21/28 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/28088 ,  H01L21/324 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/4966

Abstract: Embodiments are directed to a method and resulting structures for a dual channel complementary metal-oxide-semiconductor (CMOS) having common gate stacks. A first semiconductor fin is formed on a substrate. A second semiconductor fin is formed adjacent to the first semiconductor fin on the substrate. An oxide layer is formed over the first and second semiconductor fins and annealed at a temperature effective to increase a germanium concentration of the second semiconductor fin. The annealing process is selective to the second semiconductor fin and does not increase a germanium concentration of the first semiconductor fin.

公开(公告)号：US20180331101A1

公开(公告)日：2018-11-15

申请号：US15593816

申请日：2017-05-12

Applicant: International Business Machines Corporation

Inventor： Brent A. Anderson ,  Ruqiang Bao ,  Dechao Guo ,  Vijay Narayanan

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L21/823871 ,  H01L21/823885 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7845

Abstract: A method of forming a semiconductor structure includes forming an interfacial layer surrounding at least one channel stack, forming a high-k dielectric layer surrounding the interfacial layer, and forming a metal gate layer surrounding the high-k dielectric layer. The method also includes forming a silicon layer over the metal gate layer and forming at least one additional metal layer over the silicon layer. The method further includes performing silicidation to transform at least a portion of the at least one additional metal layer and at least a portion of the silicon layer into a silicide layer. The metal gate layer, the silicon layer and the silicide layer form at least one gate electrode for a vertical transport field-effect transistor (VTFET).