公开(公告)号：US10540141B2

公开(公告)日：2020-01-21

申请号：US16229499

申请日：2018-12-21

Applicant: Imagination Technologies Limited

Inventor： Theo Alan Drane ,  Wai-Chuen Cheung

IPC: G06F7/38 ,  G06F17/50 ,  G06F7/535

Abstract: A method and apparatus are provided for manufacturing integrated circuits performing invariant integer division x/d. A desired rounding mode is provided and an integer triple (a,b,k) for this rounding mode is derived. Furthermore, a set of conditions for the rounding mode is derived. An RTL representation is then derived using the integer triple. From this a hardware layout can be derived and an integrated circuit manufactured with the derived hardware layout. When the integer triple is derived a minimum value of k for the desired rounding mode and set of conditions is also derived.

公开(公告)号：US10331405B2

公开(公告)日：2019-06-25

申请号：US15493340

申请日：2017-04-21

Applicant: Imagination Technologies Limited

Inventor： Theo Alan Drane

IPC: G06F17/11 ,  G06F7/483 ,  G06F7/552

Abstract: An accurate implementation of a polynomial using floating-point or other rounded arithmetic can be generated using a plurality of hardware logic components which each implement an input polynomial such that the zeros in the input polynomial can be determined correctly. The number of different hardware logic components that are used can be reduced by analyzing the set of input polynomials and from it generating a set of polynomial components, where each polynomial in the set of input polynomials which is not also in the set of polynomial components, can be generated from a single one of the polynomial components.

公开(公告)号：US20190034171A1

公开(公告)日：2019-01-31

申请号：US16152021

申请日：2018-10-04

Applicant: Imagination Technologies Limited

Inventor： Freddie Rupert Exall ,  Theo Alan Drane ,  Joe Buckingham

IPC: G06F7/74

CPC classification number: G06F7/74

Abstract: Methods and leading zero anticipators for estimating the number of leading zeros in a result of a fixed point arithmetic operation which is accurate to within one bit for any signed fixed point numbers. The leading zero anticipator includes an input encoding circuit which generates an encoded input string from the fixed point numbers; a window-based surrogate string generation circuit which generates a surrogate string whose leading one is an estimate of the leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string and setting corresponding bits of the surrogate string based on the examinations; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.

公开(公告)号：US10175943B2

公开(公告)日：2019-01-08

申请号：US15497373

申请日：2017-04-26

Applicant: Imagination Technologies Limited

Inventor： Theo Alan Drane ,  Thomas Michael Rose

IPC: G06F7/26 ,  H03K19/177 ,  H03K19/21 ,  G06F7/24

Abstract: An efficient hardware apparatus for calculating the maximum and/or minimum of two n-bit binary input values generates a number of separate select signals, each of which is then used to control the selection of a single bit from one of the two binary inputs. A select signal for an ith bit of the output depends upon bits [n−1, i] in each of the two binary inputs and based on the select signal the ith bit is selected from one of the two inputs.

公开(公告)号：US20170308354A1

公开(公告)日：2017-10-26

申请号：US15497373

申请日：2017-04-26

Applicant: Imagination Technologies Limited

Inventor： Theo Alan Drane ,  Thomas Michael Rose

IPC: G06F7/26 ,  H03K19/21 ,  H03K19/177

CPC classification number: G06F7/26 ,  G06F7/24 ,  H03K19/17724 ,  H03K19/21

Abstract: An efficient hardware apparatus for calculating the maximum and/or minimum of two n-bit binary input values generates a number of separate select signals, each of which is then used to control the selection of a single bit from one of the two binary inputs. A select signal for an ith bit of the output depends upon bits [n−1, i] in each of the two binary inputs and based on the select signal the ith bit is selected from one of the two inputs.

公开(公告)号：US20160097808A1

公开(公告)日：2016-04-07

申请号：US14856393

申请日：2015-09-16

Applicant: Imagination Technologies Limited

Inventor： Theo Alan Drane

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G06F17/505

Abstract: A method implements fixed-point polynomials in hardware logic. In an embodiment the method comprises distributing a defined error bound for the whole polynomial between operators in a data-flow graph for the polynomial and optimizing each operator to satisfy the part of the error bound allocated to that operator. The distribution of errors between operators is updated in an iterative process until a stop condition (such as a maximum number of iterations) is reached.

Abstract translation: 一种方法在硬件逻辑中实现定点多项式。 在一个实施例中，该方法包括在多项式的数据流图中为运算符之间的整个多项式分配定义的误差界限，并优化每个运算符以满足分配给该运算符的部分误差范围。 运算符之间的错误分布以迭代过程更新，直到达到停止条件（如最大迭代次数）为止。

公开(公告)号：US20130346927A1

公开(公告)日：2013-12-26

申请号：US13921471

申请日：2013-06-19

Applicant: Imagination Technologies Limited

Inventor： Theo Alan Drane

IPC: G06F7/523 ,  G06F17/50

CPC classification number: G06F7/523 ,  G06F7/49947 ,  G06F7/509 ,  G06F7/5338 ,  G06F17/5045

Abstract: A method is provided for a synthesising In RTL, a logic circuit and for manufacturing an integrated circuit for performing a sum of addends with faithful rounding. In this, optimisation constraints for a value of bits which may be discarded and a constant to include in a sum of addends are determined (20). Next, the maximum number of whole columns that can be removed from the sum of addends array is derived (22) and those columns are discarded (24). Next, a number of bits which can be removed from the least significant column is derived (26) and these bits are discarded (28). The constant is included in the sum of addends and a logic array synthesised in RTL (31) before manufacturing an integrated circuit.

Abstract translation: 提供了一种用于合成In RTL，逻辑电路和用于制造集成电路的方法，用于执行具有忠实舍入的加法和的总和。 在此，确定可以被丢弃的比特值的优化约束和包括在加数之和中的常数的优化约束（20）。 接下来，导出可以从加数数组的总和中删除的整个列的最大数目（22），并丢弃那些列（24）。 接下来，导出可以从最低有效列移除的位数（26），并丢弃这些位（28）。 在制造集成电路之前，常数包括在加数和RTL（31）中合成的逻辑阵列之和。

公开(公告)号：US20130103733A1

公开(公告)日：2013-04-25

申请号：US13626886

申请日：2012-09-26

Applicant: Imagination Technologies Limited

Inventor： Theo Alan Drane ,  Wai-Chuen Cheung

IPC: G06F7/38

CPC classification number: G06F7/38 ,  G06F7/535 ,  G06F17/50 ,  G06F17/5045 ,  G06F17/505

Abstract: A method and apparatus are provided for manufacturing integrated circuits performing invariant integer division x/d. A desired rounding mode is provided and an integer triple (a,b,k) for this rounding mode is derived. Furthermore, a set of conditions for the rounding mode is derived. An RTL representation is then derived using the integer triple. From this a hardware layout can be derived and an integrated circuit manufactured with the derived hardware layout. When the integer triple is derived a minimum value of k for the desired rounding mode and set of conditions is also derived.

Abstract translation: 提供了一种用于制造执行不变整数除法x / d的集成电路的方法和装置。 提供期望的舍入模式，并导出用于该舍入模式的整数三（a，b，k）。 此外，导出用于舍入模式的一组条件。 然后使用整数三进制导出RTL表示。 从这一点可以推导出硬件布局和使用派生硬件布局制造的集成电路。 当导出整数三元组时，也推导出所需舍入模式的最小值k和条件集合。

公开(公告)号：US11836460B2

公开(公告)日：2023-12-05

申请号：US17171174

申请日：2021-02-09

Applicant: Imagination Technologies Limited

Inventor： Theo Alan Drane

IPC: G06F7/535 ,  G06F30/327 ,  G06F30/34 ,  G06F7/523 ,  G06F7/38

CPC classification number: G06F7/523 ,  G06F7/38 ,  G06F7/535 ,  G06F30/327 ,  G06F30/34 ,  G06F2207/5356

Abstract: A hardware logic representation of a circuit to implement an operation to perform multiplication by an invariant rational is generated by truncating an infinite single summation array (which is represented in a finite way). The truncation is performed by identifying a repeating section and then discarding all but a finite number of the repeating sections whilst still satisfying a defined error bound. To further reduce the size of the summation array, the binary representation of the invariant rational is converted into canonical signed digit notation prior to creating the finite representation of the infinite array.

公开(公告)号：US20210271795A1

公开(公告)日：2021-09-02

申请号：US17323373

申请日：2021-05-18

Applicant: Imagination Technologies Limited

Inventor： Theo Alan Drane

IPC: G06F30/327

Abstract: A method implements fixed-point polynomials in hardware logic. In an embodiment the method comprises distributing a defined error bound for the whole polynomial between operators in a data-flow graph for the polynomial and optimizing each operator to satisfy the part of the error bound allocated to that operator. The distribution of errors between operators is updated in an iterative process until a stop condition (such as a maximum number of iterations) is reached.