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公开(公告)号：US20200097243A1
公开(公告)日：2020-03-26
申请号：US16586043
申请日：2019-09-27
Applicant: Intel Corporation
Inventor： Deepak S. Vembar , Atsuo Kuwahara , Chandrasekaran Sakthivel , Radhakrishnan Venkataraman , Brent E. Insko , Anupreet S. Kalra , Hugues Labbe , Altug Koker , Michael Apodaca , Kai Xiao , Jeffery S. Boles , Adam T. Lake , David M. Cimini , Balaji Vembu , Elmoustapha Ould-Ahmed-Vall , Jacek Kwiatkowski , Philip R. Laws , Ankur N. Shah , Abhishek R. Appu , Joydeep Ray , Wenyin Fu , Nikos Kaburlasos , Prasoonkumar Surti , Bhushan M. Borole
Abstract: An embodiment of a graphics apparatus may include a processor, memory communicatively coupled to the processor, and a collaboration engine communicatively coupled to the processor to identify a shared graphics component between two or more users in an environment, and share the shared graphics components with the two or more users in the environment. Embodiments of the collaboration engine may include one or more of a centralized sharer, a depth sharer, a shared preprocessor, a multi-port graphics subsystem, and a decode sharer. Other embodiments are disclosed and claimed.
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公开(公告)号：US10587244B2
公开(公告)日：2020-03-10
申请号：US16180604
申请日：2018-11-05
Applicant: Intel Corporation
Inventor： Bhushan M. Borole , Anupama A. Thaploo , Altug Koker , Abhishek R. Appu , Kamal Sinha , Wenyin Fu
Abstract: A pulse triggered flip flop circuit includes an exclusive OR clock generating stage that receives an input clock, data and produces an output clock pulse. The stage produces a output clock pulse that only goes away when the data is fully captured. The stage disables the output clock pulse only when the data is fully captured. Moreover, the circuit only toggles when the input data changes, reducing power consumption in some embodiments.
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公开(公告)号：US10579121B2
公开(公告)日：2020-03-03
申请号：US15477029
申请日：2017-04-01
Applicant: Intel Corporation
Inventor： Altug Koker , Abhishek R. Appu , Kiran C. Veernapu , Joydeep Ray , Balaji Vembu , Prasoonkumar Surti , Kamal Sinha , Eric J. Hoekstra , Wenyin Fu , Nikos Kaburlasos , Bhushan M. Borole , Travis T. Schluessler , Ankur N. Shah , Jonathan Kennedy
IPC: G06F15/16 , G06F1/3209 , G06F1/3212 , G06F1/3218 , G06F1/3231 , G06F3/01 , G06F11/07 , G06F11/30
Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.
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公开(公告)号：US10319070B2
公开(公告)日：2019-06-11
申请号：US16120591
申请日：2018-09-04
Applicant: Intel Corporation
Inventor： Abhishek R. Appu , Joydeep Ray , Altug Koker , Balaji Vembu , Prasoonkumar P. Surti , Kamal Sinha , Vasanth Ranganathan , Kiran C. Veernapu , Bhushan M. Borole , Wenyin Fu
Abstract: In accordance with one embodiment each page table entry maps a variable page size (per entry), if multiple continuous virtual pages map to contiguous physical pages. This may drastically reduce the number of translation lookaside buffer (TLB) entries needed since each entry can potentially map a larger chunk of memory, in some embodiments.
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公开(公告)号：US20190035452A1
公开(公告)日：2019-01-31
申请号：US16054207
申请日：2018-08-03
Applicant: Intel Corporation
Inventor： Bhushan M. Borole , Iqbal R. Rajwani , Anupama A. Thaploo , Sunil Nekkanti , Altug Koker , Abhisek R. Appu
IPC: G11C11/4094 , G06F3/06 , G11C11/4093 , G06F13/40 , G06F9/38 , G11C11/4074
CPC classification number: G11C11/4094 , G06F3/0604 , G06F3/0659 , G06F3/0673 , G06F9/30123 , G06F9/30141 , G06F9/3851 , G06F9/3867 , G06F9/3887 , G06F12/0868 , G06F12/0897 , G06F12/1027 , G06F12/109 , G06F13/4068 , G11C11/4074 , G11C11/4093 , G11C11/419 , Y02D10/14 , Y02D10/151
Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.
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Patent Agency Ranking
公开(公告)号：US20190026856A1
公开(公告)日：2019-01-24
申请号：US16120591
申请日：2018-09-04
Applicant: Intel Corporation
Inventor： Abhishek R. Appu , Joydeep Ray , Altug Koker , Balaji Vembu , Prasoonkumar P. Surti , Kamal Sinha , Vasanth Ranganathan , Kiran C. Veernapu , Bhushan M. Borole , Wenyin Fu
Abstract: In accordance with one embodiment each page table entry maps a variable page size (per entry), if multiple continuous virtual pages map to contiguous physical pages. This may drastically reduce the number of translation lookaside buffer (TLB) entries needed since each entry can potentially map a larger chunk of memory, in some embodiments.
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公开(公告)号：US10158346B2
公开(公告)日：2018-12-18
申请号：US15488628
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Bhushan M. Borole , Anupama A. Thaploo , Altug Koker , Abhishek R. Appu , Kamal Sinha , Wenyin Fu
Abstract: A pulse triggered flip flop circuit includes an exclusive OR clock generating stage that receives an input clock, data and produces an output clock pulse. The stage produces a output clock pulse that only goes away when the data is fully captured. The stage disables the output clock pulse only when the data is fully captured. Moreover, the circuit only toggles when the input data changes, reducing power consumption in some embodiments.
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公开(公告)号：US20180300260A1
公开(公告)日：2018-10-18
申请号：US15488840
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Abhishek R. Appu , Joydeep Ray , James A. Valerio , Altug Koker , Prasoonkumar P. Surti , Balaji Vembu , Wenyin FU , Bhushan M. Borole , Kamal Sinha
IPC: G06F12/128 , G06F12/0811 , G06F13/40 , G06T1/20
Abstract: A hybrid hierarchical cache is implemented at the same level in the access pipeline, to get the faster access behavior of a smaller cache and, at the same time, a higher hit rate at lower power for a larger cache, in some embodiments. A split cache at the same level in the access pipeline includes two caches that work together. In the hybrid, split, low level cache (e.g., L1) evictions are coordinated locally between the two L1 portions, and on a miss to both L1 portions, a line is allocated from a larger L2 cache to the smallest L1 cache.
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公开(公告)号：US20180300045A1
公开(公告)日：2018-10-18
申请号：US15488998
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Prasoonkumar Surti , Wenyin Fu , Nikos Kaburlasos , Bhushan M. Borole
IPC: G06F3/0484 , G06T1/20 , G09G5/10
Abstract: Methods and apparatus relating to techniques for provision of active window rendering optimization and display are described. In an embodiment, a processor is caused to render an active portion of a display device prior to an inactive portion of the display device based at least in part on comparison of a determined size of the active portion of the display device with a threshold value. Furthermore, the active portion of the display device may include a portion of the display device that is being viewed by a user or otherwise a portion of the display device with which a user is interacting. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20180293695A1
公开(公告)日：2018-10-11
申请号：US15483236
申请日：2017-04-10
Applicant: Intel Corporation
Inventor： Saurabh Sharma , Abhishek Venkatesh , Travis T. Schluessler , Prasoonkumar Surti , Altug Koker , Aravindh V. Anantaraman , Pattabhiraman P. K. , Abhishek R. Appu , Joydeep Ray , Kamal Sinha , Vasanth Ranganathan , Bhushan M. Borole , Wenyin Fu , Eric J. Hoekstra , Linda L. Hurd
CPC classification number: G06T1/20 , G06T1/60 , G06T15/005
Abstract: A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.
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