公开(公告)号：US20220216611A1

公开(公告)日：2022-07-07

申请号：US17705182

申请日：2022-03-25

Applicant: Intel Corporation

Inventor： Jimin Yao ,  Robert L. Sankman ,  Shawna M. Liff ,  Sri Chaitra Jyotsna Chavali ,  William J. Lambert ,  Zhichao Zhang

IPC: H01Q9/04 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/66

Abstract: In accordance with disclosed embodiments, there is an antenna package using a ball attach array to connect an antenna and base substrates of the package. One example is an RF module package including an RF antenna package having a stack material in between a top and a bottom antenna layer to form multiple antenna plane surfaces, a base package having alternating patterned conductive and dielectric layers to form routing through the base package, and a bond between a bottom surface of the antenna package and to a top surface of the base package.

公开(公告)号：US11276634B2

公开(公告)日：2022-03-15

申请号：US16607601

申请日：2017-05-23

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Rahul N. Manepalli ,  David Unruh ,  Frank Truong ,  Kyu Oh Lee ,  Junnan Zhao ,  Sri Chaitra Jyotsna Chavali

IPC: H01L23/498 ,  H01L23/14 ,  H01L21/48

Abstract: Disclosed herein are integrated circuit (IC) package substrates formed with a dielectric bi-layer, and related devices and methods. In some embodiments, an IC package substrate is fabricated by: forming a raised feature on a conductive layer; forming a dielectric bi-layer on the conductive layer, where the dielectric bi-layer includes a first sub-layer having a first material property and a second sub-layer having a second material property, and where the top surface of the second sub-layer is substantially planar with the top surface of the raised feature; and removing the first sub-layer until the second material property is detected to reveal the conductive feature. In some embodiments, an IC package substrate is fabricated by: forming a dielectric bi-layer on a patterned conductive layer, where the first sub-layer is less susceptible to removal than the second sub-layer; forming an opening in the dielectric bi-layer; etching; and forming a via having vertical sidewalls.

公开(公告)号：US20210351116A1

公开(公告)日：2021-11-11

申请号：US17379724

申请日：2021-07-19

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  William James Lambert ,  Zhichao Zhang ,  Sri Chaitra Jyotsna Chavali ,  Stephen Andrew Smith ,  Michael James Hill ,  Zhenguo Jiang

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H05K1/18 ,  H01L23/00 ,  H01L25/10 ,  H01L25/065 ,  H05K7/02 ,  H01L21/56

Abstract: Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.

公开(公告)号：US11004792B2

公开(公告)日：2021-05-11

申请号：US16145804

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Sri Chaitra Jyotsna Chavali

IPC: H01L23/532 ,  H01L23/538 ,  H01L23/00 ,  H01L23/373 ,  H01L23/492

Abstract: Described are microelectronic devices including a substrate formed with multiple build-up layers, and having at least one build-up layer formed of a fiber-containing material. A substrate can include a buildup layers surrounding an embedded die, or outward of the build-up layer surrounding the embedded die that includes a fiber-containing dielectric. Multiple build-up layers located inward from a layer formed of a fiber-containing dielectric will be formed of a fiber-free dielectric.

公开(公告)号：US20200312675A1

公开(公告)日：2020-10-01

申请号：US16901172

申请日：2020-06-15

Applicant: Intel Corporation

Inventor： Sri Chaitra Jyotsna Chavali ,  Siddharth K. Alur ,  Lilia May ,  Amanda E. Amanda

IPC: H01L21/48 ,  H01L23/498

Abstract: Generally discussed herein are systems, devices, and methods that include an organic high density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low density buildup layers on a core, conductive interconnect material of the one or more low density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high density buildup layers on an exposed low density buildup layer of the one or more low density buildup layers, conductive interconnect material of the high density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low density buildup layers, and forming another low density buildup layer on and around an exposed high density buildup layer of the one or more high density buildup layers.

公开(公告)号：US10685850B2

公开(公告)日：2020-06-16

申请号：US16305743

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Sri Chaitra Jyotsna Chavali ,  Siddharth K. Alur ,  Lilia May ,  Amanda E. Schuckman

IPC: H01L21/48 ,  H01L23/498

Abstract: Generally discussed herein are systems, devices, and methods that include an organic high density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low density buildup layers on a core, conductive interconnect material of the one or more low density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high density buildup layers on an exposed low density buildup layer of the one or more low density buildup layers, conductive interconnect material of the high density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low density buildup layers, and forming another low density buildup layer on and around an exposed high density buildup layer of the one or more high density buildup layers.

公开(公告)号：US20200075473A1

公开(公告)日：2020-03-05

申请号：US16607601

申请日：2017-05-23

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Rahul N. Manepalli ,  David Unruh ,  Frank Truong ,  Kyu Oh Lee ,  Junnan Zhao ,  Sri Chaitra Jyotsna Chavali

IPC: H01L23/498 ,  H01L23/14 ,  H01L21/48

Abstract: Disclosed herein are integrated circuit (IC) package substrates formed with a dielectric bi-layer, and related devices and methods. In some embodiments, an IC package substrate is fabricated by: forming a raised feature on a conductive layer; forming a dielectric bi-layer on the conductive layer, where the dielectric bi-layer includes a first sub-layer having a first material property and a second sub-layer having a second material property, and where the top surface of the second sub-layer is substantially planar with the top surface of the raised feature; and removing the first sub-layer until the second material property is detected to reveal the conductive feature. In some embodiments, an IC package substrate is fabricated by: forming a dielectric bi-layer on a patterned conductive layer, where the first sub-layer is less susceptible to removal than the second sub-layer; forming an opening in the dielectric bi-layer; etching; and forming a via having vertical sidewalls.