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公开(公告)号:US20200006651A1
公开(公告)日:2020-01-02
申请号:US16022685
申请日:2018-06-28
Applicant: Intel Corporation
Inventor: Daniel H. MORRIS , Uygar E. AVCI , Ian A. YOUNG
IPC: H01L45/00 , H01L23/528 , H03K19/0175 , H01L27/24
Abstract: A routing structure is disclosed. A first wiring line coupled to a programming access device and a routing block driver and receiver enabling device and a second wiring line coupled to a programming access device and a routing block driver and receiver enabling device. An insulator-metal-transistor device that includes a top electrode, a middle electrode and a bottom electrode, coupled at the intersection of the first wiring line and the second wiring line.
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公开(公告)号:US20180122478A1
公开(公告)日:2018-05-03
申请号:US15567942
申请日:2015-05-28
Applicant: Intel Corporation
Inventor: Daniel H. MORRIS , Uygar E. AVCI , Ian A. YOUNG
IPC: G11C14/00 , G11C11/22 , H01L27/11502
CPC classification number: G11C14/0072 , G11C11/221 , G11C11/2259 , G11C11/2273 , G11C11/2275 , G11C14/0027 , H01L27/11502
Abstract: Described is an apparatus which comprises: a first access transistor controllable by a write word-line (WWL); a second access transistor controllable by a read word-line (RWL); and a ferroelectric cell coupled to the first and second access transistors, wherein the ferroelectric cell is programmable via the WWL and readable via the RWL. Described is a method which comprises: driving a WWL, coupled to a gate terminal of a first access transistor, to cause the first access transistor to turn on; and driving a WBL coupled to a source/drain terminal of the first access transistor, the driven WBL to charge or discharge a storage node coupled to the first access transistor when the first access transistor is turned on, wherein the ferroelectric cell is coupled to the storage node and programmable according to the charged or discharged storage node.
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公开(公告)号:US20250113547A1
公开(公告)日:2025-04-03
申请号:US18375064
申请日:2023-09-29
Applicant: Intel Corporation
Inventor: Chia-Ching LIN , Tao CHU , Chiao-Ti HUANG , Guowei XU , Robin CHAO , Feng ZHANG , Yue ZHONG , Yang ZHANG , Ting-Hsiang HUNG , Kevin P. O’BRIEN , Uygar E. AVCI , Carl H. NAYLOR , Mahmut Sami KAVRIK , Andrey VYATSKIKH , Rachel STEINHARDT , Chelsey DOROW , Kirby MAXEY
IPC: H01L29/786 , H01L29/06 , H01L29/24 , H01L29/417 , H01L29/66 , H01L29/775
Abstract: Integrated circuit structures having internal spacers for 2D channel materials, and methods of fabricating integrated circuit structures having internal spacers for 2D channel materials, are described. For example, an integrated circuit structure includes a stack of two-dimensional (2D) material nanowires. A gate structure is vertically around the stack of 2D material nanowires. Internal gate spacers are between vertically adjacent ones of the stack of 2D material nanowires and laterally adjacent to the gate structure. The 2D material nanowires are recessed relative to the internal gate spacers. Conductive contact structures are at corresponding ends of the stack of 2D material nanowires, the conductive contact structures adjacent to the internal gate spacers and vertically overlapping with the internal gate spacers.
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公开(公告)号:US20230113614A1
公开(公告)日:2023-04-13
申请号:US17485185
申请日:2021-09-24
Applicant: Intel Corporation
Inventor: Kevin P. O'BRIEN , Chelsey DOROW , Carl NAYLOR , Kirby MAXEY , Sudarat LEE , Ashish Verma PENUMATCHA , Uygar E. AVCI , Scott B. CLENDENNING , Urusa ALAAN , Tristan A. TRONIC
IPC: H01L29/423 , H01L29/786 , H01L27/12
Abstract: Thin film transistors having CMOS functionality integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a first device including a first two-dimensional (2D) material layer, and a first gate stack around the first 2D material layer. The first gate stack has a gate electrode around a gate dielectric layer. A second device is stacked on the first device. The second device includes a second 2D material layer, and a second gate stack around the second 2D material layer. The second gate stack has a gate electrode around a gate dielectric layer. The second 2D material layer has a composition different than a composition of the first 2D material layer.
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公开(公告)号:US20230102900A1
公开(公告)日:2023-03-30
申请号:US17485162
申请日:2021-09-24
Applicant: Intel Corporation
Inventor: Nafees A. KABIR , Shriram SHIVARAMAN , Seung Hoon SUNG , Uygar E. AVCI
IPC: H01L29/786 , H01L29/78 , H01L29/66 , H01L21/4763
Abstract: A method of fabricating an integrated circuit structure comprises depositing an oxide insulator layer over a substrate having fins. A gate trench is formed within the oxide insulator layer with the fins extending above a surface of the oxide insulator layer within the gate trench. A semiconducting oxide material is deposited to conformally cover the oxide insulator layer, including on top surfaces and sidewalls of both the gate trench and the fins. A gate material is deposited to conformally cover the semiconducting oxide material, including on top surfaces and sidewalls of both the gate trench and the fins. An angled etch is performed to remove the gate material selective to the semiconducting oxide material from sidewalls of the gate trench, but not from sidewalls of the fins.
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公开(公告)号:US20230102695A1
公开(公告)日:2023-03-30
申请号:US17485301
申请日:2021-09-24
Applicant: Intel Corporation
Inventor: Carl H. NAYLOR , Kirby MAXEY , Kevin P. O'BRIEN , Chelsey DOROW , Sudarat LEE , Ashish Verma PENUMATCHA , Uygar E. AVCI , Matthew V. METZ , Scott B. CLENDENNING
IPC: H01L29/45 , H01L29/417 , H01L27/088
Abstract: Embodiments of the disclosure are directed to advanced integrated circuit (IC) structure fabrication and, in particular, to IC structures with graphene contacts. Other embodiments may be disclosed or claimed.
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公开(公告)号:US20230101760A1
公开(公告)日:2023-03-30
申请号:US17485225
申请日:2021-09-24
Applicant: Intel Corporation
Inventor: Kevin P. O'BRIEN , Uygar E. AVCI , Scott B. CLENDENNING , Chelsey DOROW , Sudarat LEE , Kirby MAXEY , Carl H. NAYLOR , Tristan A. TRONIC , Shriram SHIVARAMAN , Ashish Verma PENUMATCHA
IPC: H01L27/092 , H01L27/11 , H01L29/06 , H01L29/423 , H01L29/417 , H01L23/48 , H01L29/786
Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a first transistor on a first level, and a second transistor on a second level above the first level. In an embodiment, an insulating layer is between the first level and the second level, and a via passes through the insulating layer, and electrically couples the first transistor to the second transistor. In an embodiment, the first transistor and the second transistor comprise a first channel, and a second channel over the first channel. In an embodiment, the first second transistor further comprise a gate structure between the first channel and the second channel, a source contact on a first end of the first channel and the second channel, and a drain contact on a second end of the first channel and the second channel.
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48.
公开(公告)号:US20230101370A1
公开(公告)日:2023-03-30
申请号:US17485181
申请日:2021-09-24
Applicant: Intel Corporation
Inventor: Sudarat LEE , Chelsey DOROW , Kevin P. O'BRIEN , Carl H. NAYLOR , Kirby MAXEY , Charles MOKHTARZADEH , Ashish Verma PENUMATCHA , Scott B. CLENDENNING , Uygar E. AVCI
IPC: H01L29/76 , H01L29/06 , H01L29/24 , H01L29/423 , H01L29/49 , H01L29/786 , H01L21/02 , H01L29/66
Abstract: Thin film transistors having multi-layer gate dielectric structures integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a two-dimensional (2D) material layer above a substrate. A gate stack is over the 2D material layer, the gate stack having a first side opposite a second side, and the gate stack having a gate electrode around a gate dielectric structure. A first gate spacer is on the 2D material layer and adjacent to the first side of the gate stack. A second gate spacer is on the 2D material layer and adjacent to the second side of the gate stack, wherein the first gate spacer and the second gate spacer are continuous with a layer of the gate dielectric structure. A first conductive structure is coupled to the 2D material layer and adjacent to the first gate spacer. A second conductive structure is coupled to the 2D material layer and adjacent to the second gate spacer.
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公开(公告)号:US20230100713A1
公开(公告)日:2023-03-30
申请号:US17485302
申请日:2021-09-24
Applicant: Intel Corporation
Inventor: Chelsey DOROW , Kevin P. O'BRIEN , Carl H. NAYLOR , Kirby MAXEY , Sudarat LEE , Ashish Verma PENUMATCHA , Uygar E. AVCI
IPC: H01L29/76 , H01L29/24 , H01L29/06 , H01L29/423 , H01L29/45 , H01L29/786
Abstract: Embodiments of the disclosure are directed to advanced integrated circuit (IC) structure fabrication and, in particular, IC structures with an improved two-dimensional (2D) channel architecture. Other embodiments may be disclosed or claimed.
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公开(公告)号:US20230097641A1
公开(公告)日:2023-03-30
申请号:US17485311
申请日:2021-09-24
Applicant: Intel Corporation
Inventor: Christopher M. NEUMANN , Nazila HARATIPOUR , Sou-Chi CHANG , Uygar E. AVCI , Shriram SHIVARAMAN
IPC: H01L27/11514 , H01L27/11504 , H01L21/768
Abstract: Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, ferroelectric three-dimensional (3D) memory architectures. Other embodiments may be disclosed or claimed.
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