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公开(公告)号：US20150379398A1
公开(公告)日：2015-12-31
申请号：US14846289
申请日：2015-09-04
摘要： Embodiments of the invention relate to a scalable neural hardware for the noisy-OR model of Bayesian networks. One embodiment comprises a neural core circuit including a pseudo-random number generator for generating random numbers. The neural core circuit further comprises a plurality of incoming electronic axons, a plurality of neural modules, and a plurality of electronic synapses interconnecting the axons to the neural modules. Each synapse interconnects an axon with a neural module. Each neural module receives incoming spikes from interconnected axons. Each neural module represents a noisy-OR gate. Each neural module spikes probabilistically based on at least one random number generated by the pseudo-random number generator unit.
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公开(公告)号：US20150379396A1
公开(公告)日：2015-12-31
申请号：US14846259
申请日：2015-09-04
CPC分类号： G06N3/0635 , G06N3/04 , G06N3/049 , G06N3/063 , G06N3/08
摘要： Embodiments of the invention relate to providing transposable access to a synapse array using a recursive array layout. One embodiment comprises maintaining synaptic weights for multiple synapses connecting multiple axons and multiple neurons, wherein the synaptic weights are maintained based on a recursive array layout. The recursive array layout facilitates transposable access to the synaptic weights. A neuronal spike event between an axon and a neuron is communicated via a corresponding connecting synapse by accessing the synaptic weight of the corresponding connecting synapse in the recursive array layout.
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公开(公告)号：US09195903B2
公开(公告)日：2015-11-24
申请号：US14265268
申请日：2014-04-29
CPC分类号： G06K9/4671 , G06K9/00744 , G06K9/4604 , G06K9/4652 , G06K9/4676 , G06K9/66 , G06N3/049 , G06N3/063
摘要： Embodiments of the invention provide a method of visual saliency estimation comprising receiving an input sequence of image frames. Each image frame has one or more channels, and each channel has one or more pixels. The method further comprises, for each channel of each image frame, generating corresponding neural spiking data based on a pixel intensity of each pixel of the channel, generating a corresponding multi-scale data structure based on the corresponding neural spiking data, and extracting a corresponding map of features from the corresponding multi-scale data structure. The multi-scale data structure comprises one or more data layers, wherein each data layer represents a spike representation of pixel intensities of a channel at a corresponding scale. The method further comprises encoding each map of features extracted as neural spikes.
摘要翻译： 本发明的实施例提供一种视觉显着性估计方法，包括接收图像帧的输入序列。 每个图像帧具有一个或多个通道，并且每个通道具有一个或多个像素。 该方法还包括对于每个图像帧的每个通道，基于通道的每个像素的像素强度生成相应的神经峰值数据，基于相应的神经峰值数据生成相应的多尺度数据结构，并且提取相应的 从相应的多尺度数据结构的特征图。 多尺度数据结构包括一个或多个数据层，其中每个数据层表示相应尺度的通道的像素强度的尖峰表示。 该方法还包括对作为神经尖峰提取的特征的每个图进行编码。
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公开(公告)号：US09152916B2
公开(公告)日：2015-10-06
申请号：US14491816
申请日：2014-09-19
CPC分类号： G06N3/04 , G06F9/44505 , G06N3/049 , G06N3/063 , G06N3/088
摘要： Embodiments of the invention provide a neural core circuit comprising a synaptic interconnect network including plural electronic synapses for interconnecting one or more source electronic neurons with one or more target electronic neurons. The interconnect network further includes multiple axon paths and multiple dendrite paths. Each synapse is at a cross-point junction of the interconnect network between a dendrite path and an axon path. The core circuit further comprises a routing module maintaining routing information. The routing module routes output from a source electronic neuron to one or more selected axon paths. Each synapse provides a configurable level of signal conduction from an axon path of a source electronic neuron to a dendrite path of a target electronic neuron.
摘要翻译： 本发明的实施例提供了一种包括突触互连网络的神经核心电路，其包括用于将一个或多个源电子神经元与一个或多个目标电子神经元相互连接的多个电子突触。 互连网络还包括多个轴突路径和多个树枝状路径。 每个突触处于互连网络在树枝状路径和轴突路径之间的交叉点处。 核心电路还包括维护路由信息的路由模块。 路由模块将源电子神经元的输出路由到一个或多个选择的轴突路径。 每个突触提供从源电子神经元的轴突路径到目标电子神经元的枝晶路径的可配置水平的信号传导。
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45.发明申请INITIALIZING AND TESTING INTEGRATED CIRCUITS WITH SELECTABLE SCAN CHAINS WITH EXCLUSIVE-OR OUTPUTS 有权具有选择性扫描链的独立或输出的初始化和测试集成电路公开(公告)号：US20150276867A1
公开(公告)日：2015-10-01
申请号：US14229739
申请日：2014-03-28
发明人： Rodrigo Alvarez-Icaza Rivera , John V. Arthur , Andrew S. Cassidy , Bryan L. Jackson , Paul A. Merolla , Dharmendra S. Modha , Jun Sawada
IPC分类号： G01R31/3177
CPC分类号： G01R31/31703 , G01R31/3172 , G01R31/31725 , G01R31/3177 , G01R31/318516 , G01R31/318519 , G01R31/318558 , G01R31/318561 , G01R31/3187
摘要： Embodiments of the invention provide a scan test system for an integrated circuit comprising multiple processing elements. The system comprises at least one scan input component and at least one scan clock component. Each scan input component is configured to provide a scan input to at least two processing elements. Each scan clock component is configured to provide a scan clock signal to at least two processing elements. The system further comprises at least one scan select component for selectively enabling a scan of at least one processing element. Each processing element is configured to scan in a scan input and scan out a scan output when said the processing element is scan-enabled. The system further comprises an exclusive-OR tree comprising multiple exclusive-OR logic gates. The said exclusive-OR tree generates a parity value representing a parity of all scan outputs scanned out from all scan-enabled processing elements.
摘要翻译： 本发明的实施例提供了一种用于包括多个处理元件的集成电路的扫描测试系统。 该系统包括至少一个扫描输入部件和至少一个扫描时钟部件。 每个扫描输入组件被配置为向至少两个处理元件提供扫描输入。 每个扫描时钟分量被配置为向至少两个处理元件提供扫描时钟信号。 该系统还包括至少一个扫描选择部件，用于选择性地启用至少一个处理元件的扫描。 每个处理元件被配置为在扫描输入中扫描并且当所述处理元件被扫描启用时扫描出扫描输出。 该系统还包括包含多个异或逻辑门的异或树。 所述异或树生成表示从所有启用扫描的处理元件扫描的所有扫描输出的奇偶校验值的奇偶校验值。
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公开(公告)号：US09087742B2
公开(公告)日：2015-07-21
申请号：US13798446
申请日：2013-03-13
IPC分类号： H01L27/12 , A61B5/04 , H01L21/768
CPC分类号： H01L27/1203 , A61B5/04001 , A61B2562/028 , A61B2562/046 , H01L21/76898
摘要： A high density micro-electrode array includes a transistor layer including a plurality of access transistors and a substrate in operable communication with the transistor layer including, wherein at least a portion of the substrate includes a plurality of trenches. The system includes a plurality of electrodes at least partially located in the plurality of trenches, wherein each of the plurality of electrodes is connected to at least one of the plurality of access transistors and wherein each of the electrodes is separated by a distance less than approximately one microns.
摘要翻译： 高密度微电极阵列包括包括多个存取晶体管的晶体管层和与晶体管层可操作地连通的衬底，其中至少一部分衬底包括多个沟槽。 该系统包括至少部分地位于多个沟槽中的多个电极，其中多个电极中的每一个电极连接到多个存取晶体管中的至少一个，并且其中每个电极分开一个小于大约 一微米。
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公开(公告)号：US20150039546A1
公开(公告)日：2015-02-05
申请号：US13957805
申请日：2013-08-02
发明人： Rodrigo Alvarez-Icaza , John V. Arthur , Andrew S. Cassidy , Bryan L. Jackson , Paul A. Merolla , Dharmendra S. Modha , Jun Sawada
IPC分类号： G06N3/04
CPC分类号： G06N3/063 , G06N3/0472 , G06N3/049
摘要： One embodiment provides a system comprising a memory device for maintaining deterministic neural data relating to a digital neuron and a logic circuit for deterministic neural computation and stochastic neural computation. Deterministic neural computation comprises processing a neuronal state of the neuron based on the deterministic neural data maintained. Stochastic neural computation comprises generating stochastic neural data relating to the neuron and processing the neuronal state of the neuron based on the stochastic neural data generated.
摘要翻译： 一个实施例提供一种系统，其包括用于维持与数字神经元有关的确定性神经数据的存储器装置和用于确定性神经计算和随机神经计算的逻辑电路。 确定性神经计算包括基于保持的确定性神经数据处理神经元的神经元状态。 随机神经计算包括生成与神经元有关的随机神经数据，并根据生成的随机神经数据处理神经元的神经元状态。
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公开(公告)号：US20140222740A1
公开(公告)日：2014-08-07
申请号：US13683234
申请日：2012-11-21
发明人： Rodrigo Alvarez-Icaza Rivera , John V. Arthur , Andrew S. Cassidy , Paul A. Merolla , Dharmendra S. Modha
IPC分类号： G06N3/04
摘要： Embodiments of the invention relate to a neural network system comprising a single memory block for multiple neurosynaptic core modules. One embodiment comprises a neural network system including a memory array that maintains information for multiple neurosynaptic core modules. Each neurosynaptic core module comprises multiple neurons. The neural network system further comprises at least one logic circuit. Each logic circuit receives neuronal firing events targeting a neurosynaptic core module of the neural network system, and said logic circuit integrates the firing events received based on information maintained in said memory for said neurosynaptic core module.
摘要翻译： 本发明的实施例涉及包括用于多个神经突触核心模块的单个存储块的神经网络系统。 一个实施例包括神经网络系统，其包括维持多个神经突触核心模块的信息的存储器阵列。 每个神经突触核心模块包括多个神经元。 神经网络系统还包括至少一个逻辑电路。 每个逻辑电路接收针对神经网络系统的神经突触核心模块的神经元触发事件，并且所述逻辑电路基于所述神经突触核心模块的所述存储器中保存的信息来集成所接收的触发事件。
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公开(公告)号：US11521085B2
公开(公告)日：2022-12-06
申请号：US16842035
申请日：2020-04-07
发明人： Jun Sawada , Dharmendra S. Modha , Andrew S. Cassidy , John V. Arthur , Tapan K. Nayak , Carlos O. Otero , Brian Taba , Filipp A. Akopyan , Pallab Datta
摘要： Neural inference chips for computing neural activations are provided. In various embodiments, a neural inference chip comprises at least one neural core, a memory array, an instruction buffer, and an instruction memory. The instruction buffer has a position corresponding to each of a plurality of elements of the memory array. The instruction memory provides at least one instruction to the instruction buffer. The instruction buffer advances the at least one instruction between positions in the instruction buffer. The instruction buffer provides the at least one instruction to at least one of the plurality of elements of the memory array from its associated position in the instruction buffer when the memory of the at least one of the plurality of elements contains data associated with the at least one instruction. Each element of the memory array provides a data block from its memory to its horizontal buffer in response to the arrival of an associated instruction from the instruction buffer. The horizontal buffer of each element of the memory array provides a data block to the horizontal buffer of another of the elements of the memory array or to the at least one neural core.
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公开(公告)号：US20220129742A1
公开(公告)日：2022-04-28
申请号：US17077709
申请日：2020-10-22
发明人： Alexander Andreopoulos , Dharmendra S. Modha , Carmelo Di Nolfo , Myron D. Flickner , Andrew Stephen Cassidy , Brian Seisho Taba , Pallab Datta , Rathinakumar Appuswamy , Jun Sawada
摘要： Simulation and validation of neural network systems is provided. In various embodiments, a description of an artificial neural network is read. A directed graph is constructed comprising a plurality of edges and a plurality of nodes, each of the plurality of edges corresponding to a queue and each of the plurality of nodes corresponding to a computing function of the neural network system. A graph state is updated over a plurality of time steps according to the description of the neural network, the graph state being defined by the contents of each of the plurality of queues. Each of a plurality of assertions is tested at each of the plurality of time steps, each of the plurality of assertions being a function of a subset of the graph state. Invalidity of the neural network system is indicated for each violation of one of the plurality of assertions.
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