公开(公告)号：US20220367691A1

公开(公告)日：2022-11-17

申请号：US17660729

申请日：2022-04-26

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Kentaro MIURA ,  Akihiro HANADA ,  Takaya TAMARU

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/4757 ,  H01L21/4763 ,  H01L21/426 ,  H01L29/786

Abstract: According to one embodiment, a method of manufacturing a semiconductor device, includes forming a first insulating layer, an oxide semiconductor layer, a second insulating layer, a buffer layer and a metal layer sequentially on a base, forming a patterned resist on the metal layer, etching the buffer layer and the metal layer using the resist as a mask to expose an upper surface of the second insulating layer, reducing a volume of the resist to expose an upper surface along a side surface of the metal layer, etching the metal layer using the resist as a mask, to form a gate electrode and to expose an upper surface of the buffer layer, and carrying out ion implantation on the oxide semiconductor layer using the gate electrode as a mask.

公开(公告)号：US20220246764A1

公开(公告)日：2022-08-04

申请号：US17724512

申请日：2022-04-20

Applicant: Japan Display Inc.

Inventor： Isao SUZUMURA ,  Hajime WATAKABE ,  Akihiro HANADA ,  Ryo ONODERA ,  Tomoyuki ITO

IPC: H01L29/786

Abstract: The present invention addresses the problem of: realizing a TFT that uses an oxide semiconductor and that is capable of maintaining stable characteristics even in the case where the TFT is miniaturized; and realizing a display device that has high-definition pixels using such a TFT. To solve this problem, the present invention has the following configuration. A semiconductor device including an oxide semiconductor TFT formed using an oxide semiconductor film 109, the semiconductor device being characterized in that: the channel length of the oxide semiconductor TFT is 1.3 to 2.3 μm; and the sheet resistance of a source region 1092 and a drain region 1091 of the oxide semiconductor film 109 is 1.4 to 20 KΩ/□.

公开(公告)号：US20220238558A1

公开(公告)日：2022-07-28

申请号：US17583231

申请日：2022-01-25

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Kentaro MIURA ,  Akihiro HANADA

IPC: H01L27/12 ,  H01L29/786

Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a polycrystalline silicon semiconductor, an oxide semiconductor, a gate electrode located directly above the oxide semiconductor, a first conductive layer in contact with the polycrystalline silicon semiconductor via a first contact hole, and in contact with the oxide semiconductor via a second contact hole and a second conductive layer stacked on the first conductive layer between the first contact hole and the second contact hole. The first conductive layer includes an extending portion extending from the second contact hole toward the gate electrode. The second conductive layer is not stacked on the extending portion. The first conductive layer is thinner than the second conductive layer.

公开(公告)号：US20220190164A1

公开(公告)日：2022-06-16

申请号：US17549882

申请日：2021-12-14

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Kentaro MIURA ,  Toshinari SASAKI ,  Takeshi SAKAI ,  Akihiro HANADA ,  Masashi TSUBUKU

IPC: H01L29/786 ,  H01L29/423

Abstract: According to one embodiment, a semiconductor device includes an oxide semiconductor. The oxide semiconductor includes a first edge portion and a second edge portion intersecting a gate electrode, a first area overlapping the gate electrode, a second area along the first edge portion, a third area along the second edge portion, a fourth area the first edge portion, a fifth area along the second edge portion, a sixth area surrounded by the first area, the second area and the third area, and a seventh area surrounded by the first area, the fourth area and the fifth area. The first area, the second area and the third area, the fourth area and the fifth area have a higher resistivity than those of the sixth area and the seventh area.

公开(公告)号：US20220181493A1

公开(公告)日：2022-06-09

申请号：US17542515

申请日：2021-12-06

Applicant: Japan Display Inc.

Inventor： Kentaro MIURA ,  Hajime WATAKABE ,  Ryo ONODERA

IPC: H01L29/786 ,  H01L29/66

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a first insulating layer above a polycrystalline silicon semiconductor, forming an oxide semiconductor on the first insulating layer, forming a second insulating layer on the oxide semiconductor, forming contact holes penetrating to the polycrystalline silicon semiconductor in insulating layers including the first insulating layer and the second insulating layer, forming a metal film on the second insulating layer, forming a patterned resist on the metal film, etching the metal film using the resist as a mask, performing ion implantation into the oxide semiconductor without removing the resist, and removing the resist.

公开(公告)号：US20220165826A1

公开(公告)日：2022-05-26

申请号：US17533127

申请日：2021-11-23

Applicant: Japan Display Inc.

Inventor： Akihiro HANADA ,  Kentaro MIURA ,  Hajime WATAKABE ,  Ryo ONODERA

IPC: H01L27/32 ,  H01L51/56

Abstract: According to one embodiment, in a display device, a first transistor includes a first semiconductor layer, in which a first source region includes a first region in contact a the first source electrode and a first drain region includes a second region in contact with a first drain electrode, the first source and drain regions, the first region, and the second region each include a first impurity element, and, in a region close to an interface between the first semiconductor layer and a first insulating layer, a concentration of the first impurity element included in the first and second regions is higher than a concentration of the first impurity element included in the first source region and the first drain region.

公开(公告)号：US20200333652A1

公开(公告)日：2020-10-22

申请号：US16918453

申请日：2020-07-01

Applicant: Japan Display Inc.

Inventor： Akihiro HANADA ,  Isao SUZUMURA ,  Hajime WATAKABE

IPC: G02F1/1333 ,  G02F1/1368 ,  G02F1/1335 ,  G02F1/1362 ,  H01L27/12 ,  G09F9/30 ,  H05K1/18 ,  G02F1/1339 ,  H01L27/32 ,  H01L51/00

Abstract: The purpose of the invention is to realize the flexible display device of high reliability; specifically in a structure that a bending area is in a terminal area, and in that disconnection of the wiring does not occur in the bending area. The concrete structure is that: a display device having a display area, a driving circuit area and a bending area comprising: a first thin film transistor and a first interlayer insulating film are formed in the display area, a second thin film transistor and a second interlayer insulating film are formed in the driving circuit area, terminal wirings to connects the display area and the driving circuit area are formed in the bending area.

公开(公告)号：US20170200829A1

公开(公告)日：2017-07-13

申请号：US15388720

申请日：2016-12-22

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Tomoyuki ARIYOSHI ,  Akihiro HANADA

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/24

CPC classification number: H01L29/78606 ,  G02F1/136213 ,  G02F1/1368 ,  G02F2201/121 ,  G02F2201/123 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/7869

Abstract: According to one embodiment, a thin-film transistor includes a first insulating film, an oxide semiconductor layer provided on the first insulating film and a second insulating film provided on the oxide semiconductor layer, and at least one of the first insulating film and the second insulating film includes a first region in contact with the oxide semiconductor layer and a second region further distant from the oxide semiconductor layer than the first region, and the second region has an argon concentration higher than that of the first region.

公开(公告)号：US20150380560A1

公开(公告)日：2015-12-31

申请号：US14725361

申请日：2015-05-29

Applicant: Japan Display Inc.

Inventor： Miyuki ISHIKAWA ,  Arichika ISHIDA ,  Masayoshi FUCHI ,  Hajime WATAKABE ,  Takashi OKADA

IPC: H01L29/786 ,  H01L29/417 ,  H01L21/441 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L21/441 ,  H01L21/465 ,  H01L21/467 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/3272 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78633 ,  H01L29/78696

Abstract: According to one embodiment, a semiconductor device includes contact holes passing through a source region of a drain region of an interlayer insulating film and oxide semiconductor layer to reach an insulating substrate, wherein a source electrode and a drain electrode are formed inside the contact holes, respectively.

Abstract translation: 根据一个实施例，半导体器件包括穿过层间绝缘膜和氧化物半导体层的漏极区域的源极区域的接触孔，以到达绝缘基板，其中源极电极和漏电极形成在接触孔内部， 分别。

公开(公告)号：US20250113619A1

公开(公告)日：2025-04-03

申请号：US18890900

申请日：2024-09-20

Applicant: Japan Display Inc.

Inventor： Akihiro HANADA ,  Hajime WATAKABE

IPC: H01L27/12 ,  G02F1/1368 ,  H01L29/786

Abstract: A semiconductor device includes a first gate electrode, an oxide semiconductor layer including a first oxide semiconductor having a polycrystalline structure over the first gate electrode, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, and a second gate electrode overlapping the first gate electrode and the oxide semiconductor layer over the source electrode and the drain electrode. The second gate electrode includes a second oxide semiconductor having a polycrystalline structure. The second gate electrode is electrically connected to the first gate electrode.