摘要:
In a metal gate replacement process, a cup-shaped gate metal oxide dielectric may have a vertical portion that may be exposed to a silicon ion implantation. As a result of the implantation, the dielectric constant of a vertical portion may be reduced, reducing fringe capacitance.
摘要:
A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, and forming a masking layer on a first part of the high-k gate dielectric layer. After forming a first metal layer on the masking layer and on an exposed second part of the high-k gate dielectric layer, the masking layer is removed. A second metal layer is then formed on the first metal layer and on the first part of the high-k gate dielectric layer.
摘要:
A Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region.
摘要:
Strained channel field effect transistors may have a threshold voltage shift. This threshold voltage shift may be compensated for by adjusting channel doping. But this also adversely affects mobility. The threshold voltage shift may be compensated, without adversely affecting mobility, by tailoring the workfunction of a metal gate electrode used in the transistor to adequately compensate for that threshold voltage shift. For example, in some embodiments, an appropriate metal may be selected with a slightly higher workfunction or, in other cases, the workfunction of a selected metal may be adjusted by, for example, doping the metal gate electrode with a material which increases the workfunction of the gate electrode.
摘要:
A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer that contacts a metal oxide layer. The metal oxide layer is generated by forming a metal layer, then oxidizing the metal layer.
摘要:
A method for making a semiconductor device is described. That method comprises adding nitrogen to a silicon dioxide layer to form a nitrided silicon dioxide layer on a substrate. After forming a sacrificial layer on the nitrided silicon dioxide layer, the sacrificial layer is removed to generate a trench. A high-k gate dielectric layer is formed on the nitrided silicon dioxide layer within the trench, and a metal gate electrode is formed on the high-k gate dielectric layer.
摘要:
A method for making a titanium carbide layer is described. That method comprises alternately introducing a carbon containing precursor and a titanium containing precursor into a chemical vapor deposition reactor, while a substrate is maintained at a selected temperature. The reactor is operated for a sufficient time, and pulse times are selected for the carbon containing precursor and the titanium containing precursor, to form a titanium carbide layer of a desired thickness and workfunction on the substrate.
摘要:
In a metal gate replacement process, strain may be selectively induced in the channels of NMOS and PMOS transistors. For example, a material having a higher coefficient of thermal expansion than the substrate may be used to form the gate electrodes of PMOS transistors. A material with a lower coefficient of thermal expansion than that of the substrate may be used to form the gate electrodes of NMOS transistors.
摘要:
Gate dielectrics formed of silicates of hafnium or zirconium dioxide may be formed by atomic layer deposition. The precursors for the atomic layer deposition may include an oxidant, a silicate precursor, and a zirconium or hafnium precursor.
摘要:
Replacement metal gates may be formed by removing a polysilicon layer from a gate structure. The gate structure may be formed by patterning the polysilicon layer and depositing a spacer layer over the gate structure such that the spacer layer has a first polish rate. The spacer layer is then etched to form a sidewall spacer. An interlayer dielectric is applied over the gate structure with the sidewall spacer. The interlayer dielectric has a second polish rate higher than the first polish rate. In one embodiment, the interlayer dielectric has a lower polish rate than that of oxide.