公开(公告)号：US20100269266A1

公开(公告)日：2010-10-28

申请号：US12656985

申请日：2010-02-22

Applicant: Sang Up Lee ,  Sung Jin Kim ,  Sang Yeon Pyo ,  Hong Seok Ko ,  Jae Hong Kim ,  Myung Sun Kang

Inventor： Sang Up Lee ,  Sung Jin Kim ,  Sang Yeon Pyo ,  Hong Seok Ko ,  Jae Hong Kim ,  Myung Sun Kang

IPC: D06F33/00 ,  D06F31/00

CPC classification number: D06F33/02 ,  D06F29/00

Abstract: A washing machine and a control method thereof are disclosed. The washing machine has a plurality of washing tubs to clean laundry in different ways classified according to capacity and types of clothing. Different washing tubs simultaneously stop operations or are stopped at different times spaced apart from each other by a predetermined time, although washing tubs have different washing conditions (e.g., different input times of laundry, different amounts of laundry, different washing courses, etc.) when laundry is cleaned using the washing tubs.

Abstract translation: 公开了洗衣机及其控制方法。 洗衣机具有多个洗涤桶，以根据衣物的容量和类型分类的不同方式清洗衣物。 尽管洗涤桶具有不同的洗涤条件（例如，不同的衣物输入时间，不同的衣物量，不同的洗涤程序等），不同的洗涤桶同时停止操作或者在彼此间隔开的不同时间停止预定的时间。 当使用洗涤桶清洗衣物时。

公开(公告)号：US20100254195A1

公开(公告)日：2010-10-07

申请号：US12801505

申请日：2010-06-11

Applicant: Kyoung Lae Cho ,  Seung-Hwan Song ,  Yoon Dong Park ,  Jun Jin Kong ,  Jae Hong Kim

Inventor： Kyoung Lae Cho ,  Seung-Hwan Song ,  Yoon Dong Park ,  Jun Jin Kong ,  Jae Hong Kim

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G11C16/32 ,  G11C16/349 ,  G11C29/00 ,  G11C2211/5634

Abstract: Memory devices and/or methods that may estimate characteristics of multi-bit cell are provided. A memory device may include: a multi-bit cell array; a monitoring unit to extract a threshold voltage change over time value for reference threshold voltage states selected from a plurality of threshold voltage states corresponding to data stored in the multi-bit cell array; and an estimation unit to estimate a threshold voltage change over time values for the plurality of threshold voltage states based on the extracted threshold voltage change. Through this, it is possible to monitor a change over time of threshold voltages of a memory cell.

Abstract translation: 提供了可以估计多位单元特性的存储器件和/或方法。 存储器设备可以包括：多位单元阵列; 监测单元，用于提取从对应于存储在多位单元阵列中的数据的多个阈值电压状态中选择的参考阈值电压状态的时间值的阈值电压变化; 以及估计单元，用于基于所提取的阈值电压变化来估计所述多个阈值电压状态的时间值的阈值电压变化。 由此，可以监视存储单元的阈值电压随时间的变化。

公开(公告)号：US07738293B2

公开(公告)日：2010-06-15

申请号：US12213944

申请日：2008-06-26

Applicant: Kyoung Lae Cho ,  Yoon Dong Park ,  Jun Jin Kong ,  Jong Han Kim ,  Jae Hong Kim ,  Young Hwan Lee ,  Heeseok Eun ,  Seung-Hwan Song

Inventor： Kyoung Lae Cho ,  Yoon Dong Park ,  Jun Jin Kong ,  Jong Han Kim ,  Jae Hong Kim ,  Young Hwan Lee ,  Heeseok Eun ,  Seung-Hwan Song

IPC: G11C16/04 ,  G11C29/04

CPC classification number: G11C11/5628 ,  G11C29/00 ,  G11C2216/14

Abstract: A memory programming apparatuses and/or methods are provided. The memory programming apparatus may include a data storage unit, a first counting unit, an index storage unit and/or a programming unit. The data storage unit may be configured to store a data page. The first counting unit may be configured to generate index information by counting a number of cells included in at least one reference threshold voltage state based on the data page. The index storage unit may be configured to store the generated index information. The programming unit may be configured to store the data page in the data storage unit and store the generated index information in the index storage unit. The first counting unit may send the generated index information to the programming unit. The memory programming apparatus can monitor distribution states of threshold voltages in memory cells.

Abstract translation: 提供了存储器编程设备和/或方法。 存储器编程装置可以包括数据存储单元，第一计数单元，索引存储单元和/或编程单元。 数据存储单元可以被配置为存储数据页。 第一计数单元可以被配置为通过基于数据页计数包括在至少一个参考阈值电压状态中的单元的数量来生成索引信息。 索引存储单元可以被配置为存储所生成的索引信息。 编程单元可以被配置为将数据页存储在数据存储单元中，并将生成的索引信息存储在索引存储单元中。 第一计数单元可以将生成的索引信息发送到编程单元。 存储器编程装置可以监视存储器单元中阈值电压的分布状态。

公开(公告)号：US20090307566A1

公开(公告)日：2009-12-10

申请号：US12475640

申请日：2009-06-01

Applicant: Jong Seon No ,  Beom Kyu Shin ,  Seok Il Youn ,  Jae Dong Yang ,  Jun Jin Kong ,  Jae Hong Kim ,  Yong June Kim ,  Kyoung Lae Cho

Inventor： Jong Seon No ,  Beom Kyu Shin ,  Seok Il Youn ,  Jae Dong Yang ,  Jun Jin Kong ,  Jae Hong Kim ,  Yong June Kim ,  Kyoung Lae Cho

IPC: H03M13/15 ,  G06F11/10

CPC classification number: H03M13/1105 ,  H03M13/136 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/2906 ,  H03M13/3738 ,  H03M13/3753 ,  H04L1/0051 ,  H04L1/0057

Abstract: An iterative decoding method is disclosed and includes sequentially executing a number of iterative decoding cycles in relation to a parity check equation until the parity check equation is resolved, or a maximum number N of iterative decoding cycles is reached, during execution of the number of iterative decoding cycles, storing in a data buffer minimum estimated values for a set of variable nodes corresponding to a minimum number of bit errors, and outputting the minimum estimated values stored in the data buffer as a final decoding result when the number of iterative decoding cycles reaches N.

Abstract translation: 公开了一种迭代解码方法，并且包括相对于奇偶校验方程顺序执行多个迭代解码周期，直到奇偶校验方程被解析为止，或者在执行迭代次数期间达到迭代解码周期的最大数量N 解码周期，在数据缓冲器中存储对应于最小数量的位错误的一组可变节点的最小估计值，并且当迭代解码周期数达到时，输出存储在数据缓冲器中的最小估计值作为最终解码结果 N.

公开(公告)号：US20090287975A1

公开(公告)日：2009-11-19

申请号：US12453163

申请日：2009-04-30

Applicant: Yong June Kim ,  Jae Hong Kim ,  Jun Jin Kong ,  Kyoung Lae Cho

Inventor： Yong June Kim ,  Jae Hong Kim ,  Jun Jin Kong ,  Kyoung Lae Cho

IPC: G06F11/10 ,  G11C16/04 ,  G11C16/06 ,  G11C16/02 ,  H03M13/03

CPC classification number: G11C16/10 ,  G06F11/1072 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/3454 ,  G11C29/00 ,  G11C2211/5621 ,  G11C2211/5634

Abstract: Memory devices and/or methods of managing memory data errors are provided. A memory device detects and corrects an error bit of data read from a plurality of memory cells, and identifies a memory cell storing the detected error bit. The memory device assigns a verification voltage to each of the plurality of first memory cells, the assigned verification voltage corresponding to the corrected bit for the identified memory cell, the assigned verification voltage corresponding to the read data for the remaining memory cells. The memory device readjusts the data stored in the plurality of memory cells using the assigned verification voltage. Through this, it is possible to increase a retention period of the data of the memory device.

Abstract translation: 提供了存储器件和/或管理存储器数据错误的方法。 存储器件检测并校正从多个存储器单元读取的数据的错误位，并且识别存储检测到的错误位的存储单元。 存储装置向多个第一存储器单元中的每一个分配验证电压，对应于所识别的存储单元的校正位的分配的验证电压，对应于剩余存储单元的读取数据的分配验证电压。 存储装置使用分配的验证电压重新调整存储在多个存储单元中的数据。 由此，可以增加存储装置的数据的保持期。

公开(公告)号：US07592222B2

公开(公告)日：2009-09-22

申请号：US12147178

申请日：2008-06-26

Applicant: Eun Shil Park ,  Kwon Hong ,  Jae Hong Kim ,  Jae Hyoung Koo

Inventor： Eun Shil Park ,  Kwon Hong ,  Jae Hong Kim ,  Jae Hyoung Koo

IPC: H01L21/336

CPC classification number: H01L21/28273 ,  H01L27/11521

Abstract: The present invention relates to a method of fabricating a flash memory device. According to a method of fabricating a flash memory device in accordance with an aspect of the present invention, a semiconductor substrate over which a tunnel insulating layer and a first conductive layer are formed is provided. A first oxide layer is formed on the first conductive layer using a plasma oxidization process in a state where a back bias voltage is applied. A nitride layer is formed on the first oxide layer. A second oxide layer is formed on the nitride layer. A second conductive layer is formed on the second oxide layer.

Abstract translation: 本发明涉及一种制造闪速存储器件的方法。 根据本发明的一个方面的制造闪速存储器件的方法，提供了形成隧道绝缘层和第一导电层的半导体衬底。 在施加反向偏置电压的状态下，使用等离子体氧化工艺在第一导电层上形成第一氧化物层。 在第一氧化物层上形成氮化物层。 在氮化物层上形成第二氧化物层。 在第二氧化物层上形成第二导电层。

公开(公告)号：US20090235129A1

公开(公告)日：2009-09-17

申请号：US12230832

申请日：2008-09-05

Applicant: Heeseok Eun ,  Jae Hong Kim ,  Jun Jin Kong

Inventor： Heeseok Eun ,  Jae Hong Kim ,  Jun Jin Kong

IPC: G11C29/04 ,  G06F11/22 ,  G06F11/00

CPC classification number: G11C29/52 ,  G11C11/5642 ,  G11C29/00 ,  G11C2029/0411 ,  G11C2211/5634

Abstract: The data detecting apparatus may provide a voltage comparison unit that compares a reference voltage, associated with a specific data bit from among a plurality of data bits stored in a memory cell, with a threshold voltage in the memory cell, a detection unit that detects a value of the specific data bit based on a result of the voltage comparison unit, and a decision unit that decides whether the specific data bit is successfully detected based on whether an error occurs in the detected data. The detection unit may re-detect a value of the specific data bit based on detection information with respect to at least one of an upper data bit and a lower data bit in relation to the specific data bit, in response to a result of the decision unit.

Abstract translation: 数据检测装置可以提供电压比较单元，其将存储在存储单元中的多个数据位中的与特定数据位相关联的参考电压与存储单元中的阈值电压进行比较，检测单元检测 基于电压比较单元的结果的特定数据位的值，以及判定单元，其基于检测到的数据中是否发生错误来判定是否成功检测到特定数据位。 响应于决定的结果，检测单元可以基于关于特定数据比特的上位数据位和下位数据位中的至少一个的检测信息重新检测特定数据位的值 单元。

公开(公告)号：US07586597B2

公开(公告)日：2009-09-08

申请号：US11548453

申请日：2006-10-11

Applicant: Ji Young Yim ,  Jae Hong Kim

Inventor： Ji Young Yim ,  Jae Hong Kim

IPC: G01N21/00

CPC classification number: H01L21/76871

Abstract: A device and/or method which detects a seed layer and a device and/or method of forming layers on a semiconductor device. The device which forms layers on the semiconductor device may include a metal layer forming unit (which forms a metal layer on a wafer), a copper seed layer forming unit (which forms a copper seed layer on the metal layer), a wafer alignment device (which includes a wafer alignment unit which aligns the wafer to a predetermined position), a copper seed layer detecting unit (which is positioned above the wafer alignment unit to detect the copper seed layer formed on the wafer), and a plating unit (which forms a copper interconnection layer on the copper seed layer).

Abstract translation: 一种检测种子层的装置和/或方法，以及在半导体器件上形成层的器件和/或方法。 在半导体器件上形成层的器件可以包括金属层形成单元（其在晶片上形成金属层），铜籽晶层形成单元（在金属层上形成铜籽晶层），晶片对准装置 （其包括将晶片对准到预定位置的晶片对准单元），铜籽晶层检测单元（位于晶片对准单元上方以检测形成在晶片上的铜籽晶层），以及电镀单元（其 在铜籽晶层上形成铜互连层）。

公开(公告)号：US20090137708A1

公开(公告)日：2009-05-28

申请号：US12006144

申请日：2007-12-31

Applicant: Jae Hong Kim ,  Yun Jong Jeon

Inventor： Jae Hong Kim ,  Yun Jong Jeon

IPC: C08L53/00 ,  C08K3/34 ,  C08K3/30 ,  C08K3/26 ,  C08K5/13 ,  C08K5/524 ,  C08K5/098 ,  C08K3/22

CPC classification number: C08L23/083 ,  C08K3/013 ,  C08K3/22 ,  C08K3/30 ,  C08L9/06 ,  C08L23/0815 ,  C08L53/00 ,  C08L2666/24 ,  C08L2666/06 ,  C08L2666/08 ,  C08L2666/02 ,  C08L2666/04 ,  C08L2666/14

Abstract: The present invention relates to a polypropylene resin composition, more particularly to a composition comprising an ethylene/propylene block copolymer, an ethylene/α-olefin copolymer rubber, a styrene-based polymer rubber, a polypropylene-silicone rubber master batch, a magnesium compound and an inorganic filler.The polypropylene resin composition of the present invention exhibits superior rigidity, scratch resistance and glossiness, outstanding laser processability and low-temperature impact resistance, and also superior fluidity. Therefore, it is applicable to manufacture interior materials of a vehicle such as an instrument panel. Especially, the present invention is suitable to manufacture an air bag deployable instrument panel assembly requiring no coating.

Abstract translation: 本发明涉及一种聚丙烯树脂组合物，更具体地说涉及包含乙烯/丙烯嵌段共聚物，乙烯/α-烯烃共聚物橡胶，苯乙烯基聚合物橡胶，聚丙烯 - 硅橡胶母料，镁化合物 和无机填料。 本发明的聚丙烯树脂组合物具有优异的刚性，耐刮擦性和光泽度，突出的激光加工性和耐低温冲击性，并且还具有优异的流动性。 因此，适用于制造诸如仪表板的车辆的内部材料。 特别地，本发明适用于制造不需要涂布的气囊可展开的仪表板组件。

公开(公告)号：US20080150139A1

公开(公告)日：2008-06-26

申请号：US11930341

申请日：2007-10-31

Applicant: Jae Hong Kim

Inventor： Jae Hong Kim

IPC: H01L23/52 ,  H01L21/4763

CPC classification number: H01L21/76855 ,  H01L21/76867 ,  H01L21/76873

Abstract: Disclosed are a semiconductor device and a method for manufacturing the same, capable of improving the performance of a barrier and inhibiting a discontinuous step coverage and an overhang. The semiconductor device includes an interlayer dielectric layer having a via hole disposed on a semiconductor substrate, a first layer disposed in the via hole and including ruthenium (Ru), a second layer disposed on the first layer and including ruthenium oxide (RuO2), and a metal line disposed on the second layer and including a copper material.

Abstract translation: 公开了一种半导体器件及其制造方法，能够提高阻挡层的性能并抑制不连续的台阶覆盖和突出。 半导体器件包括具有布置在半导体衬底上的通孔的层间介质层，设置在通孔中并包括钌（Ru）的第一层，设置在第一层上的第二层，并且包含氧化钌（RuO < 2）和设置在第二层上并包括铜材料的金属线。