公开(公告)号：US08848478B2

公开(公告)日：2014-09-30

申请号：US13625104

申请日：2012-09-24

申请人： Krishnam R. Datla ,  William H. Radke ,  Robin Sarno ,  Laszlo Borbely-Bartis ,  Ken Kannampuzha

发明人： Krishnam R. Datla ,  William H. Radke ,  Robin Sarno ,  Laszlo Borbely-Bartis ,  Ken Kannampuzha

IPC分类号： G11C5/14

CPC分类号： G06F3/0625 ,  G06F3/0653 ,  G06F3/0688 ,  G11C5/14 ,  G11C16/30

摘要： The present disclosure includes apparatuses and methods for power consumption control. A number of embodiments include determining power consumption information for each phase in a combination of phases of a command, and authorizing execution of at least one of the phases in the combination based, at least partially, on the power consumption information determined for the at least one of the phases.

摘要翻译： 本公开包括用于功耗控制的装置和方法。 多个实施例包括在命令的相位组合中确定每个阶段的功率消耗信息，并且至少部分地基于至少为至少确定的功耗信息授权执行组合中的至少一个相位的功率消耗信息 其中一个阶段。

公开(公告)号：US08762629B2

公开(公告)日：2014-06-24

申请号：US13616486

申请日：2012-09-14

申请人： William H. Radke ,  Vishal Sarin ,  Jung-Sheng Hoei

发明人： William H. Radke ,  Vishal Sarin ,  Jung-Sheng Hoei

IPC分类号： G06F13/00 ,  G06F13/28

CPC分类号： G06F11/1072 ,  G06F12/0246 ,  G06F2212/7205 ,  G06F2212/7208 ,  G11C11/5628 ,  G11C29/52 ,  G11C2211/5641

摘要： Methods and apparatus for managing data storage in memory devices utilizing memory arrays of varying density memory cells. Data can be initially stored in lower density memory. Data can be further read, compacted, conditioned and written to higher density memory as background operations. Methods of data conditioning to improve data reliability during storage to higher density memory and methods for managing data across multiple memory arrays are also disclosed.

摘要翻译： 用于利用不同密度存储单元的存储器阵列来管理存储器件中的数据存储的方法和装置。 数据最初可以存储在较低密度的存储器中。 可以将数据进一步读取，压缩，调节并写入高密度存储器作为后台操作。 还公开了用于在存储到更高密度存储器期间提高数据可靠性的数据调节方法以及用于跨多个存储器阵列管理数据的方法。

公开(公告)号：US20140086000A1

公开(公告)日：2014-03-27

申请号：US13625104

申请日：2012-09-24

申请人： Krishnam R. Datla ,  William H. Radke ,  Robin Sarno ,  Laszlo Borbely-Bartis ,  Ken Kannampuzha

发明人： Krishnam R. Datla ,  William H. Radke ,  Robin Sarno ,  Laszlo Borbely-Bartis ,  Ken Kannampuzha

IPC分类号： G11C5/14

CPC分类号： G06F3/0625 ,  G06F3/0653 ,  G06F3/0688 ,  G11C5/14 ,  G11C16/30

摘要： The present disclosure includes apparatuses and methods for power consumption control. A number of embodiments include determining power consumption information for each phase in a combination of phases of a command, and authorizing execution of at least one of the phases in the combination based, at least partially, on the power consumption information determined for the at least one of the phases.

摘要翻译： 本公开包括用于功耗控制的装置和方法。 多个实施例包括在命令的相位组合中确定每个阶段的功率消耗信息，并且至少部分地基于至少为至少确定的功耗信息授权执行组合中的至少一个相位的功率消耗信息 其中一个阶段。

公开(公告)号：US08510634B2

公开(公告)日：2013-08-13

申请号：US13371683

申请日：2012-02-13

申请人： Brady L. Keays ,  Shuba Swaminathan ,  William H. Radke

发明人： Brady L. Keays ,  Shuba Swaminathan ,  William H. Radke

IPC分类号： G11C29/00

CPC分类号： G06F11/10 ,  G06F11/1048 ,  H03M13/132 ,  H03M13/1515

摘要： Methods include receiving data and an ECC code read from a memory array, generating an ECC code from the received data, and determining whether the received data is corrupted by evaluating the generated ECC code against the ECC code read from the memory array. If the received data is determined to be corrupted, a correction algorithm and a recorded likely state of a known bad/questionable bit of the received data may be used to correct error in the received data. Alternatively, if the received data is determined to be corrupted, the correction algorithm and a recorded location of a known bad/questionable bit of the received data may be used to correct error in the received data.

摘要翻译： 方法包括从存储器阵列接收数据和从其读取的ECC代码，从接收到的数据生成ECC代码，并且通过根据从存储器阵列读取的ECC代码评估所生成的ECC代码来确定接收的数据是否被破坏。 如果接收到的数据被确定为被破坏，则可以使用接收到的数据的已知的坏/可疑比特的校正算法和记录的可能状态来校正接收到的数据中的错误。 或者，如果接收到的数据被确定为已被破坏，则可以使用校正算法和接收到的数据的已知坏/可疑位的记录位置来校正接收到的数据中的错误。

公开(公告)号：US08468415B2

公开(公告)日：2013-06-18

申请号：US13570180

申请日：2012-08-08

申请人： William H. Radke

发明人： William H. Radke

IPC分类号： G11C29/00

CPC分类号： G06F11/1008 ,  G06F11/1072 ,  H03M13/256 ,  H03M13/2909

摘要： Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are used, and in another dimension, supplemental error correction codes, such as convolutional codes, are used. By using separate dimensions, the likelihood that a defect affects both error recovery techniques is lessened, thereby increasing the probability that error recovery can be performed successfully. In one example, block error correction codes are used for data stored along rows, and this data is stored in one level of multiple-level cells of the array. Supplemental error correction codes are used for data stored along columns, such as along the cells of a string, and the supplemental error correction codes are stored in a different level than the error correction codes.

公开(公告)号：US08381076B2

公开(公告)日：2013-02-19

申请号：US12897260

申请日：2010-10-04

申请人： William H. Radke

发明人： William H. Radke

IPC分类号： G11C29/00

CPC分类号： H03M13/05 ,  G06F11/1068

摘要： Improved memory devices, circuitry, and data methods are described that facilitate the detection and correction of data in memory systems or devices by increasing the data area of user data being covered by the ECC code. This averages any possible bit errors over a larger data area and allows a greater number of errors to be corrected by a combining the ECC codes in the coverage area without substantially changing the overall size of ECC codes being stored over a single sector approach. In one embodiment of the present invention, the size of the data block utilized for ECC coverage is variable and can be selected such that differing areas of the memory array or data types can have a differing ECC data coverage sizes. It is also noted that the ECC algorithm, math base or encoding scheme can also be varied between these differing areas of the memory array.

摘要翻译： 描述了改进的存储器件，电路和数据方法，其通过增加由ECC代码覆盖的用户数据的数据区域来促进对存储器系统或器件中的数据的检测和校正。 这样可以在更大的数据区域上平均任何可能的位错误，并且允许通过组合覆盖区域中的ECC码来校正更多数量的错误，而不会基本上改变通过单个扇区方法存储的ECC码的总体大小。 在本发明的一个实施例中，用于ECC覆盖的数据块的大小是可变的，并且可以选择使得存储器阵列或数据类型的不同区域可以具有不同的ECC数据覆盖尺寸。 还应注意的是，ECC算法，数学基础或编码方案也可以在存储器阵列的这些不同区域之间变化。

公开(公告)号：US20130028022A1

公开(公告)日：2013-01-31

申请号：US13190911

申请日：2011-07-26

申请人： Tommaso VALI ,  Giovanni Santin ,  Massimo Rossini ,  William H. Radke ,  Violante Moschiano

发明人： Tommaso VALI ,  Giovanni Santin ,  Massimo Rossini ,  William H. Radke ,  Violante Moschiano

IPC分类号： G11C16/10

CPC分类号： G11C16/3436 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3422

摘要： Methods for determining a program window and memory devices are disclosed. One such method for determining the program window measures an amount of program disturb experienced by a particular state and determines the program window responsive to the amount of program disturb.

摘要翻译： 公开了用于确定程序窗口和存储器件的方法。 用于确定程序窗口的一种这样的方法测量由特定状态经历的程序干扰量，并且响应于程序干扰量确定程序窗口。

公开(公告)号：US08245100B2

公开(公告)日：2012-08-14

申请号：US13267262

申请日：2011-10-06

申请人： William H. Radke

发明人： William H. Radke

IPC分类号： H03M13/00

CPC分类号： G06F11/1008 ,  G06F11/1072 ,  H03M13/256 ,  H03M13/2909

摘要： Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are used, and in another dimension, supplemental error correction codes, such as convolutional codes, are used. By using separate dimensions, the likelihood that a defect affects both error recovery techniques is lessened, thereby increasing the probability that error recovery can be performed successfully. In one example, block error correction codes are used for data stored along rows, and this data is stored in one level of multiple-level cells of the array. Supplemental error correction codes are used for data stored along columns, such as along the cells of a string, and the supplemental error correction codes are stored in a different level than the error correction codes.

摘要翻译： 设备和方法存储存储器阵列的不同维度的错误恢复数据。 例如，在一个维度中，使用块纠错码（ECC），并且在另一维度中，使用补码纠错码，例如卷积码。 通过使用单独的维度，缺陷影响两种错误恢复技术的可能性减弱，从而增加了可以成功执行错误恢复的概率。 在一个示例中，块错误校正码用于沿着行存储的数据，并且该数据被存储在阵列的多级单元中。 补充纠错码用于沿列存储的数据，例如沿着字符串的单元格，并且补充纠错码存储在与纠错码不同的电平上。

公开(公告)号：US20120147672A1

公开(公告)日：2012-06-14

申请号：US13403078

申请日：2012-02-23

申请人： William H. Radke

发明人： William H. Radke

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G06F11/1008 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C29/00 ,  G11C2211/5641

摘要： Methods, devices, modules, and systems for programming memory cells can include storing charges corresponding to a data state that represents an integer number of bits in a set of memory cells. Programming memory cells can include storing a charge in a cell of the set, where the charge corresponds to a programmed state, where the programmed state represents a fractional number of bits, and where the programmed state denotes a digit of the data state as expressed by a number in base N, where N is equal to 2B, rounded up to an integer, and where B is equal to the fractional number of bits represented by the programmed state.

摘要翻译： 用于编程存储器单元的方法，设备，模块和系统可以包括存储与在一组存储器单元中表示整数位的数据状态相对应的电荷。 编程存储器单元可以包括将电荷存储在组的单元中，其中电荷对应于编程状态，其中编程状态表示分数位数，并且其中编程状态表示数据状态的数字，如 基数N中的数，其中N等于2B，向上舍入为整数，并且其中B等于由编程状态表示的分数的位数。

公开(公告)号：US08060719B2

公开(公告)日：2011-11-15

申请号：US12127945

申请日：2008-05-28

申请人： William H. Radke ,  Michael Murray ,  Martin Ragnar Furuhjelm ,  John Geldman

发明人： William H. Radke ,  Michael Murray ,  Martin Ragnar Furuhjelm ,  John Geldman

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0246 ,  G06F2212/1016 ,  G06F2212/1036 ,  G06F2212/7201 ,  G06F2212/7211 ,  G11C16/349 ,  G11C2211/5641

摘要： Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi level memory cells. Logical addresses can be distributed between single level and multilevel memory cells based on a frequency of write operations performed. Initial storage of data corresponding to a logical address in memory can be determined by various methods including initially writing all data to single level memory or initially writing all data to multilevel memory. Other methods permit a host to direct logical address writes to single level or multilevel memory cells based on anticipated usage.

摘要翻译： 用于使用单级和多级存储器单元来管理混合存储器件中的数据存储的方法和装置。 逻辑地址可以基于执行的写操作的频率在单级和多级存储器单元之间分配。 可以通过各种方法来确定与存储器中的逻辑地址相对应的数据的初始存储，包括首先将所有数据写入单级存储器或者首先将所有数据写入多级存储器。 其他方法允许主机根据预期用途将逻辑地址写入指向单级或多级存储器单元。