公开(公告)号：US20080048268A1

公开(公告)日：2008-02-28

申请号：US11923717

申请日：2007-10-25

申请人： Louis Hsu ,  Jack Mandelman

发明人： Louis Hsu ,  Jack Mandelman

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： Semiconductor structures in which the gate electrode of a FinFET is masked from the process introducing dopant into the fin body of the FinFET to form source/drain regions and methods of fabricating such semiconductor structures. The gate doping, and hence the work function of the gate electrode, is advantageously isolated from the process that dopes the fin body to form the source/drain regions. The sidewalls of the gate electrode are covered by sidewall spacers that are formed on the gate electrode but not on the sidewall of the fin body.

摘要翻译： 其中FinFET的栅极被从引入掺杂剂的工艺掩模到FinFET的鳍状体中以形成源极/漏极区域的半导体结构以及制造这种半导体结构的方法。 栅极掺杂以及因此栅电极的功函数有利地与掺杂鳍体以形成源极/漏极区的过程隔离。 栅电极的侧壁由形成在栅电极上但不在鳍体的侧壁上的侧壁间隔物覆盖。

公开(公告)号：US20080044959A1

公开(公告)日：2008-02-21

申请号：US11925352

申请日：2007-10-26

申请人： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman

发明人： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman

IPC分类号： H01L21/86

CPC分类号： H01L21/84 ,  H01L27/0218 ,  H01L27/10841 ,  H01L27/1203 ,  H01L29/66545

摘要： A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact in the buried dielectric layer of the SOI wafer. The body contact electrically couples a semiconductor body with a channel region of the access device of one vertical memory cell and a semiconductor substrate of the SOI wafer. The body contact provides a current leakage path that reduces the impact of floating body effects upon the vertical memory cell. The body contact may be formed by an ion implantation process that modifies the stoichiometry of a region of the buried dielectric layer so that the modified region becomes electrically conductive with a relatively high resistance.

摘要翻译： 一种用于动态随机存取存储器（DRAM）单元阵列的半导体结构，其包括建立在绝缘体上半导体（SOI）晶片上的多个垂直存储单元和SOI晶片的埋入介质层中的体接触。 体接触将半导体本体与一个垂直存储单元的存取器件的沟道区和SOI晶片的半导体衬底电耦合。 身体接触提供了一种电流泄漏路径，可减少浮体对垂直记忆体的影响。 体接触可以通过离子注入工艺形成，该方法改变掩埋介电层的区域的化学计量，使得改性区域以相对较高的电阻变为导电性。

公开(公告)号：US20070278619A1

公开(公告)日：2007-12-06

申请号：US11443394

申请日：2006-05-30

申请人： Lawrence Clevenger ,  Timothy Joseph Dalton ,  Louis Hsu ,  Carl Radens ,  Vidhya Ramachandran ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Timothy Joseph Dalton ,  Louis Hsu ,  Carl Radens ,  Vidhya Ramachandran ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L29/00

CPC分类号： H01L21/84 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5223 ,  H01L27/1203 ,  H01L2924/0002 ,  Y10S438/957 ,  H01L2924/00

摘要： Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semiconductor device includes a semiconductor substrate having a front side, a back side, and a buried insulating layer interposed between the front and back sides of the substrate. An integrated circuit is formed on the front side of the semiconductor substrate, an integrated capacitor is formed on the back side of the semiconductor substrate, and an interconnection structure is formed through the buried insulating layer to connect the integrated capacitor to the integrated circuit.

摘要翻译： 提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面的高Q片上电容器，并使用晶片间互连连接到芯片正面的集成电路。 在一个方面，半导体器件包括一个半导体衬底，该半导体衬底具有介于衬底的正面和背面之间的正面，背面和掩埋绝缘层。 在半导体基板的正面形成有集成电路，在半导体基板的背面形成有集成电容器，通过埋入绝缘层形成互连结构，将集成电容器与集成电路连接起来。

公开(公告)号：US20070211527A1

公开(公告)日：2007-09-13

申请号：US11308215

申请日：2006-03-13

申请人： Louis Hsu ,  Jack Mandelman ,  Robert Wong ,  Chih-Chao Yang

发明人： Louis Hsu ,  Jack Mandelman ,  Robert Wong ,  Chih-Chao Yang

IPC分类号： G11C16/04

CPC分类号： G11C11/4125

摘要： A system and method for automatically adjusting one or more electrical parameters in a memory device, e.g., SRAM arrays. The system and method implements an SRAM sensing sub-array for accelerated collection of fail rate data for use in determining the operating point for optimum tradeoff between single event upset immunity and performance of a primary SRAM array. The accelerated fail rate data is input to an algorithm implemented for setting the SEU sensitivity of a primary SRAM memory array to a predetermined fail rate in an ionizing particle environment. The predetermined fail rate is maintained on a real-time basis in order to provide immunity to SEU consistent with optimum performance.

摘要翻译： 一种用于自动调整存储器件（例如SRAM阵列）中的一个或多个电参数的系统和方法。 该系统和方法实现SRAM感测子阵列，用于加速收集故障率数据，用于确定单个事件不起作息和主SRAM阵列性能之间的最佳权衡的操作点。 将加速失败率数据输入到在电离粒子环境中将初级SRAM存储器阵列的SEU灵敏度设定为预定故障率的算法。 为了提供符合最佳性能的SEU的免疫力，实时地维持预定的故障率。

公开(公告)号：US20070184581A1

公开(公告)日：2007-08-09

申请号：US11347332

申请日：2006-02-03

申请人： Louis Hsu ,  Rajiv Joshi ,  Jack Mandelman

发明人： Louis Hsu ,  Rajiv Joshi ,  Jack Mandelman

IPC分类号： H01L21/00

CPC分类号： H01L23/3677 ,  H01L2924/0002 ,  H01L2924/10158 ,  Y10S438/928 ,  Y10S438/96 ,  Y10S438/977 ,  H01L2924/00

摘要： A method of fabricating a semiconductor device includes etching a substrate to form a recess, the substrate being formed on a backside of a semiconductor wafer, forming pores in the substrate in an area of the recess, and forming in the recess a material having a thermal conductivity which is greater than a thermal conductivity of the substrate. In another aspect, a method of fabricating a semiconductor device includes etching a substrate formed on a backside of a semiconductor wafer to form a recess in the substrate, and forming a sputter film in the recess, the sputter film including a first material having a coefficient of thermal expansion (CTE) which is at least substantially equal to a CTE of the substrate, and a second material having a thermal conductivity which is greater than a thermal conductivity of the substrate.

摘要翻译： 一种制造半导体器件的方法包括蚀刻衬底以形成凹部，所述衬底形成在半导体晶片的背面上，在所述凹部的区域中在所述衬底中形成孔，并且在所述凹部中形成具有热 电导率大于衬底的热导率。 另一方面，制造半导体器件的方法包括蚀刻形成在半导体晶片的背面上的衬底，以在衬底中形成凹陷，并且在凹部中形成溅射膜，溅射膜包括具有系数的第一材料 的热膨胀（CTE），其至少基本上等于衬底的CTE，以及具有大于衬底的热导率的导热性的第二材料。

公开(公告)号：US20070120218A1

公开(公告)日：2007-05-31

申请号：US11290890

申请日：2005-11-30

申请人： Louis Hsu ,  Jack Mandelman ,  William Tonti ,  Chih-Chao Yang

发明人： Louis Hsu ,  Jack Mandelman ,  William Tonti ,  Chih-Chao Yang

IPC分类号： H01L29/00

CPC分类号： H01L23/5256 ,  H01L21/268 ,  H01L21/84 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure including at least one e-fuse embedded within a trench that is located in a semiconductor substrate (bulk or semiconductor-on-insulator) is provided. In accordance with the present invention, the e-fuse is in electrical contact with a dopant region that is located within the semiconductor substrate. The present invention also provides a method of fabricating such a semiconductor structure in which the embedded e-fuse is formed substantially at the same time with the trench isolation regions.

摘要翻译： 提供了包括位于半导体衬底（主体或绝缘体中半导体）的沟槽内的至少一个电子熔丝的半导体结构。 根据本发明，电熔丝与位于半导体衬底内的掺杂区电接触。 本发明还提供一种制造这种半导体结构的方法，其中嵌入式电熔丝基本上与沟槽隔离区域同时形成。

公开(公告)号：US20070048975A1

公开(公告)日：2007-03-01

申请号：US11218198

申请日：2005-09-01

申请人： Howard Chen ,  Louis Hsu ,  Jack Mandelman

发明人： Howard Chen ,  Louis Hsu ,  Jack Mandelman

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L21/76254 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207

摘要： A semiconductor processing method includes providing a substrate, forming a plurality of semiconductor layers in the substrate, each of the semiconductor layers being distinct and selected from different groups of semiconductor element types, the semiconductor layers comprising first, second, and third semiconductor layers. The method further includes forming a nitride cap layer on the second semiconductor layer prior to forming the third semiconductor layer. Semiconductor structure formed by the above method is also described.

摘要翻译： 半导体处理方法包括提供衬底，在衬底中形成多个半导体层，每个半导体层是不同的并且选自不同的半导体元件组，半导体层包括第一，第二和第三半导体层。 该方法还包括在形成第三半导体层之前在第二半导体层上形成氮化物覆盖层。 还描述了通过上述方法形成的半导体结构。

公开(公告)号：US20070046392A1

公开(公告)日：2007-03-01

申请号：US11217163

申请日：2005-09-01

申请人： Louis Hsu ,  Lowrence Clevenger ,  Timothy Dalton ,  Carl Radens ,  Keith Hon Wong ,  Chih-Chao Yang

发明人： Louis Hsu ,  Lowrence Clevenger ,  Timothy Dalton ,  Carl Radens ,  Keith Hon Wong ,  Chih-Chao Yang

IPC分类号： H01P1/10

CPC分类号： H01H50/005 ,  H01H2050/007 ,  Y10T29/4902 ,  Y10T29/49105 ,  Y10T29/49147

摘要： A MEM switch is described having a free moving element within in micro-cavity, and guided by at least one inductive element. The switch consists of an upper inductive coil; an optional lower inductive coil, each having a metallic core preferably made of permalloy; a micro-cavity; and a free-moving switching element preferably also made of magnetic material. Switching is achieved by passing a current through the upper coil, inducing a magnetic field in the coil element. The magnetic field attracts the free-moving magnetic element upwards, shorting two open wires and thus, closing the switch. When the current flow stops or is reversed, the free-moving magnetic element drops back by gravity to the bottom of the micro-cavity and the wires open. When the chip is not mounted with the correct orientation, gravity cannot be used. In such an instance, a lower coil becomes necessary to pull the free-moving switching element back and holding it at its original position.

摘要翻译： 描述了一种MEM开关，其具有在微腔内的自由移动元件，并由至少一个电感元件引导。 开关由上感应线圈组成; 可选的下感应线圈，每个具有优选由坡莫合金制成的金属芯; 微腔; 以及优选也由磁性材料制成的自由移动的开关元件。 通过使电流通过上部线圈来实现切换，从而在线圈元件中产生磁场。 磁场向上吸引自由移动的磁性元件，短路两根开放的电线，从而闭合开关。 当电流停止或反转时，自由移动的磁性元件通过重力返回到微腔的底部并且电线打开。 当芯片未正确安装时，重力不能使用。 在这种情况下，需要下部线圈将自由移动的开关元件拉回并将其保持在其原始位置。

公开(公告)号：US20070045686A1

公开(公告)日：2007-03-01

申请号：US11216387

申请日：2005-08-31

申请人： Kangguo Cheng ,  Herbert Ho ,  Louis Hsu ,  Jack Mandelman

发明人： Kangguo Cheng ,  Herbert Ho ,  Louis Hsu ,  Jack Mandelman

IPC分类号： H01L29/94

CPC分类号： G11C11/15 ,  H01L27/1203 ,  H01L43/065

摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory cell that includes (1) a semiconductor fin enclosure formed on an insulating layer of a substrate; and (2) a ferromagnetic material within the semiconductor fin enclosure. A top surface of the ferromagnetic material is below a top surface of the semiconductor fin enclosure. Numerous other aspects are provided.

摘要翻译： 在第一方面中，提供了一种第一装置。 第一装置是存储单元，其包括：（1）形成在基板的绝缘层上的半导体翅片外壳; 和（2）半导体翅片外壳内的铁磁材料。 铁磁材料的顶表面位于半导体翅片外壳的顶表面之下。 提供了许多其他方面。

公开(公告)号：US20070040276A1

公开(公告)日：2007-02-22

申请号：US11207218

申请日：2005-08-19

申请人： Chih-Chao Yang ,  Lawrence Clevenger ,  Timothy Dalton ,  Nicholas Fuller ,  Louis Hsu

发明人： Chih-Chao Yang ,  Lawrence Clevenger ,  Timothy Dalton ,  Nicholas Fuller ,  Louis Hsu

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L23/5252 ,  H01L21/76843 ,  H01L21/76844 ,  H01L2924/0002 ,  H01L2924/00

摘要： An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of leaky dielectric between interconnects. The resistance between these original interconnects starts decreasing when two adjacent interconnects are biased and causes a time-dependent dielectric breakdown, TDDB, phenomenon to occur. Decreasing of the resistance between adjacent interconnects can also be expedited via increasing the local temperature.

摘要翻译： 提供了一种抗熔丝结构，其包括掩埋的导电的，例如作为反熔丝材料的金属层以及形成这种抗熔丝结构的方法。 根据本发明，本发明的抗熔丝结构包括互连之间的漏电介质区域。 当两个相邻的互连被偏置时，这些原始互连之间的电阻开始减小，并且引起时间依赖介质击穿TDDB现象。 也可以通过增加局部温度来加速相邻互连之间的电阻的降低。